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hcs08 microcontrollers freescale.com mc9s08ac16 mc9s08ac8 mc9s08aw16a mc9s08aw8a data sheet mc9s08ac16 rev. 8 11/2009

mc9s08ac16 series features mc9s08ac16 series devices ? consumer & industrial ? mc9s08ac16 ? mc9s08ac8 ? automotive ?mc9s08aw16a ?mc9s08aw8a 8-bit hcs08 central processor unit (cpu) ? 40-mhz hcs08 cpu (central processor unit) ? 20-mhz internal bus frequency ? hc08 instruction set with added bgnd instruction ? background debugging system ? breakpoint capability to allow single breakpoint setting during in-circu it debugging (plus two more breakpoints in on-chip debug module) ? debug module containing two comparators and nine trigger modes. eight deep fifo for storing change-of-flow addresses and event-only data. debug module supports both tag and force breakpoints. ? support for up to 32 interrupt/reset sources memory options ? up to 16 kb of on-chip in-circuit programmable flash memory with block protection and security options ? up to 1 kb of on-chip ram clock source options ? clock source options include crystal, resonator, external clock, or internally generated clock with precision nvm trimming system protection ? optional computer operating properly (cop) reset with option to run from independent internal clock source or bus clock ? low-voltage detection with reset or interrupt ? illegal opcode detection with reset ? illegal address detection with reset power-saving modes ? wait plus two stops peripherals ? adc ? 8-channel, 10-bit analog-to-digital converter with automatic compare function ? sci ? two serial communications interface modules with optional 13-bit break ? spi ? serial peripheral interface module ? iic ? inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baud rates with reduced loading ? timers ? three 16-bit timer/pulse-width modulator (tpm) modules ? two 2-channel and one 4-channel; each has selectable input capture, output compare, and edge-aligned pwm capability on each channel. each timer module may be configured for buffered, centered pwm (cpwm) on all channels ? kbi ? 7-pin keyboard interrupt module input/output ? up to 38 general-purpose input/output (i/o) pins ? software selectable pullups on ports when used as inputs ? software selectable slew rate control on ports when used as outputs ? software selectable drive strength on ports when used as outputs ? master reset pin and power-on reset (por) ? internal pullup on reset , irq, and bkgd/ms pins to reduce customer system cost package options ? 48-pin quad flat no-lead package (qfn) ? 44-pin low-profile quad flat package (lqfp) ? 42-pin shrink dual-in-line package (sdip) ? 32-pin low-profile quad flat package (lqfp)

mc9s08ac16 series data sheet covers mc9s08ac16 mc9s08ac8 mc9s08aw16a mc9s08aw8a mc9s08ac16 rev. 8 11/2009
mc9s08ac16 series data sheet, rev. 8 6 freescale semiconductor revision history to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision number revision date description of changes 0 12/2007 initial release. 1 12/2007 updated the package designators for the 32 lqfp and 44 lqfp to be lc and ld respectively. 2 2/2008 corrected the spi block module to be v3. 3 3/2008 ac market launch . verified that the adc temp sensor values were correct. 4 5/2008 incorporated general release edits and updates, revised the stop2 and stop3 max values, added the rohs logo, and updated the back cover addresses. 5 6/2008 corrected the note in the tpm introduction. 6 7/2008 changed all instances of s9s08awxxa to mc9s08awxxa except in appendix b. added 42sdip package option. 7 5/2009 corrected spi registers in ta b l e 4 - 2 . added v bg in ta bl e a - 6 . corrected title of ta b l e 6 - 3 , figure 6-13 , figure 6-14 , ta b l e 6 - 5 and figure 6-19 . added errata for the following sections: ? throughout (remove stop1 instances) ? ta b l e 4 - 1 ? ta b l e 4 - 2 ? section 9.2, ?keyboard pin sharing ? ? section 9.3, ?features ? ta b l e a - 6 ? ta b l e a - 7 ? figure a-12 8 11/20/2009 updated the whole document for mc9s08aw16 a/mc9s08aw8a to support the third tpm module. updated the tpm 1 channel to 4 for the 32-pin packages in the ta b l e 1 - 1 . updated the bit 2 of irqsc register in the ta bl e 4 - 2 . updated the temp sensor voltage in the ta bl e a - 9 . this product incorporates superflash ? technology licensed from sst. freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2007-2009. all rights reserved.
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 7 list of chapters chapter title page chapter 1 introduction............. .................................... ............................. 19 chapter 2 pins and connection s ................................ ............................. 25 chapter 3 modes of operatio n .................................... ............................. 35 chapter 4 memory .......................... .................................... ....................... 41 chapter 5 resets, interrupts, and system configur ation ..................... 63 chapter 6 parallel input/outp ut .................................. ............................. 81 chapter 7 central processor unit (s08cpuv2) ......... ........................... 107 chapter 8 internal clock generato r (s08icgv4) ....... ........................... 127 chapter 9 keyboard interrupt (s 08kbiv1) ................. ........................... 153 chapter 10 timer/pwm (s08tpmv 3) .................................. ..................... 159 chapter 11 serial communications in terface (s08sciv 4)..................... 189 chapter 12 serial peripheral inte rface (s08spiv3) ....................... ......... 209 chapter 13 inter-integrated circui t (s08iicv2) ............ ........................... 225 chapter 14 analog-to-digital conv erter (s08adc10v 1)........................ 243 chapter 15 development support . ......................... ........................ ......... 271 appendix a electrical characteristi cs and timing speci fications ....... 293 appendix b ordering information an d mechanical dr awings............... 319

mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 9 contents section number title page chapter 1 introduction 1.1 overview ................................................................................................................... ......................19 1.2 mcu block diagrams ......................................................................................................... ............20 1.3 system clock di stribution .................................................................................................. ............22 chapter 2 pins and connections 2.1 introducti on ............................................................................................................... ......................25 2.2 device pin assi gnment ...................................................................................................... .............25 2.3 recommended system connections ............................................................................................. ..30 2.3.1 power (v dd , 2 x v ss , v ddad , v ssad ) ...........................................................................32 2.3.2 oscillator (xtal, extal) ..............................................................................................32 2.3.3 reset .............................................................................................................................. 32 2.3.4 background/mode select (bkgd/ms) ............................................................................33 2.3.5 adc reference pins (v refh , v refl ) .............................................................................33 2.3.6 external interrupt pin (irq) ............................................................................................. 33 2.3.7 general-purpose i/o and peripheral ports ........................................................................34 chapter 3 modes of operation 3.1 introducti on ............................................................................................................... ......................35 3.2 features ................................................................................................................... ........................35 3.3 run mode ................................................................................................................... .....................35 3.4 active backgr ound mode ..................................................................................................... ..........35 3.5 wait mode .................................................................................................................. .....................36 3.6 stop modes ................................................................................................................. .....................36 3.6.1 stop2 mode ............................................................................................................... ........37 3.6.2 stop3 mode ............................................................................................................... ........38 3.6.3 active bdm enabled in stop mode .................................................................................38 3.6.4 lvd enabled in st op mode ..............................................................................................39 3.6.5 on-chip peripheral modules in stop modes ....................................................................39 chapter 4 memory 4.1 mc9s08ac16 series memory map ............................................................................................... 41 4.1.1 reset and interrupt vect or assignments ...........................................................................42
mc9s08ac16 series data sheet, rev. 8 10 freescale semiconductor section number title page 4.2 register addresses a nd bit assignments ..................................................................................... ...43 4.3 ram ........................................................................................................................ ........................49 4.4 flash ...................................................................................................................... ......................50 4.4.1 features ................................................................................................................. ............50 4.4.2 program and erase times .................................................................................................5 0 4.4.3 program and erase command execution .........................................................................51 4.4.4 burst program ex ecution .................................................................................................. 52 4.4.5 access erro rs ............................................................................................................ ........54 4.4.6 flash block prot ection ..................................................................................................5 4 4.4.7 vector redire ction ....................................................................................................... .....55 4.5 security ................................................................................................................... .........................55 4.6 flash registers and control bits ........................................................................................... ......57 4.6.1 flash clock divider re gister (fcdiv) ........................................................................57 4.6.2 flash options register (fopt and nvopt) ................................................................58 4.6.3 flash configuration re gister (fcnfg) .......................................................................59 4.6.4 flash protection register (fprot and nvprot) ......................................................60 4.6.5 flash status register (fstat) ......................................................................................60 4.6.6 flash command register (fcmd) ...............................................................................61 chapter 5 resets, interrupts, and system configuration 5.1 introducti on ............................................................................................................... ......................63 5.2 features ................................................................................................................... ........................63 5.3 mcu reset .................................................................................................................. ....................63 5.4 computer operating prope rly (cop) watchdog .............................................................................64 5.5 interrupts ................................................................................................................. ........................65 5.5.1 interrupt stack frame .................................................................................................... ...66 5.5.2 external interrupt re quest (irq) pin ...............................................................................66 5.5.3 interrupt vectors, sources , and local ma sks ...................................................................67 5.6 low-voltage detect (lvd) system ............................................................................................ ....69 5.6.1 power-on reset op eration ...............................................................................................69 5.6.2 lvd reset oper ation ...................................................................................................... ..69 5.6.3 lvd interrupt op eration .................................................................................................. .69 5.6.4 low-voltage warning (lvw) ...........................................................................................69 5.7 real-time interr upt (rti) .................................................................................................. .............69 5.8 mclk output ................................................................................................................ .................70 5.9 reset, interrupt, and system contro l registers and control bits ...................................................70 5.9.1 interrupt pin request status a nd control register (irqsc) ............................................71 5.9.2 system reset status register (srs) .................................................................................72 5.9.3 system background debug force re set register (sbdfr) ............................................73 5.9.4 system options register (sopt) .....................................................................................74 5.9.5 system mclk control re gister (smc lk) .....................................................................75
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 11 section number title page 5.9.6 system device identification re gister (sdidh, sdidl) ................................................75 5.9.7 system real-time interrupt status and control register (srtisc) ................................76 5.9.8 system power management status a nd control 1 register (spmsc1) ...........................77 5.9.9 system power management status a nd control 2 register (spmsc2) ...........................79 5.9.10 system options register 2 (sopt2) ................................................................................80 chapter 6 parallel input/output 6.1 introducti on ............................................................................................................... ......................81 6.2 features ................................................................................................................... ........................83 6.3 pin descriptions ........................................................................................................... ...................83 6.3.1 port a ................................................................................................................... .............83 6.3.2 port b ................................................................................................................... .............84 6.3.3 port c ................................................................................................................... .............84 6.3.4 port d ................................................................................................................... .............85 6.3.5 port e ................................................................................................................... .............85 6.3.6 port f ................................................................................................................... ..............86 6.3.7 port g ................................................................................................................... .............86 6.4 parallel i/o control ....................................................................................................... ..................87 6.5 pin control ................................................................................................................ ......................88 6.5.1 internal pullup enable ................................................................................................... ...88 6.5.2 output slew rate c ontrol enable .....................................................................................88 6.5.3 output drive strength select ............................................................................................8 8 6.6 pin behavior in stop modes ................................................................................................. ...........89 6.7 parallel i/o and pin control regi sters ..................................................................................... .......89 6.7.1 port a i/o registers (ptad and ptadd) ........................................................................89 6.7.2 port a pin control registers (ptape, ptase, ptads) .................................................90 6.7.3 port b i/o registers (ptbd and ptbdd) ........................................................................92 6.7.4 port b pin control registers (ptbpe, ptbse, ptbds) .................................................93 6.7.5 port c i/o registers (ptcd and ptcdd) ........................................................................94 6.7.6 port c pin control registers (ptcpe, ptcse, ptcds) .................................................95 6.7.7 port d i/o registers (ptdd and ptddd) .......................................................................97 6.7.8 port d pin control registers (ptdpe, ptdse, ptdds) ................................................98 6.7.9 port e i/o registers (pted and ptedd) ........................................................................99 6.7.10 port e pin control registers (ptepe, ptese, pteds) ................................................100 6.7.11 port f i/o registers (p tfd and ptfdd) .......................................................................102 6.7.12 port f pin control register s (ptfpe, ptfse, ptfds) .................................................103 6.7.13 port g i/o registers (ptgd and ptgdd) .....................................................................104 6.7.14 port g pin control registers (ptgpe, ptgse, ptgds) ..............................................105
mc9s08ac16 series data sheet, rev. 8 12 freescale semiconductor section number title page chapter 7 central processor unit (s08cpuv2) 7.1 introducti on ............................................................................................................... ....................107 7.1.1 features ................................................................................................................. ..........107 7.2 programmer?s model a nd cpu registers .....................................................................................10 8 7.2.1 accumulator (a) .......................................................................................................... ...108 7.2.2 index register (h:x) ..................................................................................................... .108 7.2.3 stack pointer (sp) ....................................................................................................... ....109 7.2.4 program counter (pc) ....................................................................................................1 09 7.2.5 condition code register (ccr) .....................................................................................109 7.3 addressing modes ........................................................................................................... ..............110 7.3.1 inherent addressing mode (inh) ................................................................................... 111 7.3.2 relative addressing mode (rel) .................................................................................. 111 7.3.3 immediate addressing mode (imm) .............................................................................. 111 7.3.4 direct addressing mo de (dir) ...................................................................................... 111 7.3.5 extended addressing mode (ext) ................................................................................ 111 7.3.6 indexed addressing mode .............................................................................................. 111 7.4 special oper ations ......................................................................................................... ................112 7.4.1 reset seque nce ........................................................................................................... ....113 7.4.2 interrupt sequence ....................................................................................................... ...113 7.4.3 wait mode op eration ...................................................................................................... 114 7.4.4 stop mode oper ation ...................................................................................................... 114 7.4.5 bgnd instru ction ......................................................................................................... ..114 7.5 hcs08 instruction set summary .............................................................................................. ....115 chapter 8 internal clock generator (s08icgv4) 8.1 introducti on ............................................................................................................... ....................129 8.1.1 features ................................................................................................................. ..........129 8.1.2 modes of oper ation ....................................................................................................... .130 8.1.3 block diag ram ............................................................................................................ ....131 8.2 external signal de scription ................................................................................................ ..........131 8.2.1 extal ? external reference cl ock / oscillator input ................................................131 8.2.2 xtal ? oscillator output ............................................................................................131 8.2.3 external clock connections ...........................................................................................132 8.2.4 external crystal/resona tor connectio ns ........................................................................132 8.3 register definition ........................................................................................................ ................132 8.3.1 icg control register 1 (icgc1) ....................................................................................133 8.3.2 icg control register 2 (icgc2) ....................................................................................134 8.3.3 icg status register 1 (icgs1) .......................................................................................135 8.3.4 icg status register 2 (icgs2) .......................................................................................136 8.3.5 icg filter registers (i cgfltu, icgfltl) ..................................................................136
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 13 section number title page 8.3.6 icg trim register (icgtrm) ........................................................................................137 8.4 functional description ..................................................................................................... .............137 8.4.1 off mode (o ff) ........................................................................................................... .....138 8.4.2 self-clocked mode (scm) .............................................................................................138 8.4.3 fll engaged, internal cl ock (fei) mode .....................................................................139 8.4.4 fll engaged internal unlocked ....................................................................................140 8.4.5 fll engaged internal locked ........................................................................................140 8.4.6 fll bypassed, external cl ock (fbe) mode ..................................................................140 8.4.7 fll engaged, external clock (fee) mode ...................................................................140 8.4.8 fll lock and loss-of-lock detection ..........................................................................141 8.4.9 fll loss-of-clock detection .........................................................................................142 8.4.10 clock mode requi rements .............................................................................................143 8.4.11 fixed frequenc y clock ................................................................................................... 144 8.4.12 high gain oscillator .................................................................................................... ...144 8.5 initialization/applicat ion informat ion ..................................................................................... .....144 8.5.1 introducti on ............................................................................................................. ........144 8.5.2 example #1: external crystal = 32 khz, bus frequency = 4.19 mhz ...........................146 8.5.3 example #2: external crystal = 4 mhz, bus frequency = 20 mhz ..............................148 8.5.4 example #3: no external crystal c onnection, 5.4 mhz bus frequency ......................150 8.5.5 example #4: internal clock generator trim ..................................................................152 chapter 9 keyboard interrupt (s08kbiv1) 9.1 introducti on ............................................................................................................... ....................153 9.2 keyboard pin sharing ....................................................................................................... ............153 9.3 features ................................................................................................................... ......................153 9.3.1 kbi block di agram ........................................................................................................ 155 9.4 register definition ........................................................................................................ ................155 9.4.1 kbi status and control register (kbisc) .....................................................................156 9.4.2 kbi pin enable regi ster (kbipe) ..................................................................................157 9.5 functional description ..................................................................................................... .............157 9.5.1 pin enables .............................................................................................................. .......157 9.5.2 edge and level se nsitivity .............................................................................................15 7 9.5.3 kbi interrupt c ontrols ................................................................................................... .158 chapter 10 timer/pwm (s08tpmv3) 10.1 introducti on .............................................................................................................. .....................159 10.2 features .................................................................................................................. .......................159 10.3 tpmv3 differences from pr evious versions ................................................................................16 1 10.3.1 migrating from tpmv1 ..................................................................................................16 3 10.3.2 features ................................................................................................................ ...........164
mc9s08ac16 series data sheet, rev. 8 14 freescale semiconductor section number title page 10.3.3 modes of oper ation ...................................................................................................... ..164 10.3.4 block diag ram ........................................................................................................... .....165 10.4 signal desc ription ........................................................................................................ .................167 10.4.1 detailed signal descriptions ..........................................................................................16 7 10.5 register definition ....................................................................................................... .................171 10.5.1 tpm status and control re gister (tpmxs c) ................................................................171 10.5.2 tpm-counter registers (t pmxcnth:tpmxcntl) ....................................................172 10.5.3 tpm counter modulo register s (tpmxmodh:tpmxmodl) ....................................173 10.5.4 tpm channel n status and cont rol register (tpmxcnsc) ..........................................174 10.5.5 tpm channel value register s (tpmxcnvh:tpmxcnvl) ..........................................176 10.6 functional description .................................................................................................... ..............177 10.6.1 counter ................................................................................................................. ...........178 10.6.2 channel mode se lection ...... ...........................................................................................1 79 10.7 reset overview ............................................................................................................ .................183 10.7.1 general ................................................................................................................. ...........183 10.7.2 description of rese t operation .......................................................................................183 10.8 interrupts ................................................................................................................ .......................183 10.8.1 general ................................................................................................................. ...........183 10.8.2 description of interr upt operation .................................................................................183 10.9 the differences from tpm v2 to tpm v3 ....................................................................................1 85 chapter 11 serial communications interface (s08sciv4) 11.1 introducti on .............................................................................................................. .....................189 11.1.1 features ................................................................................................................ ...........191 11.1.2 modes of op eration ...................................................................................................... ..191 11.1.3 block diag ram ........................................................................................................... .....192 11.2 register definition ....................................................................................................... .................194 11.2.1 sci baud rate registers (scixbdh, scixbdl) ..........................................................194 11.2.2 sci control register 1 (scixc1) ...................................................................................195 11.2.3 sci control register 2 (scixc2) ...................................................................................196 11.2.4 sci status register 1 (scixs1) ......................................................................................197 11.2.5 sci status register 2 (scixs2) ......................................................................................199 11.2.6 sci control register 3 (scixc3) ...................................................................................200 11.2.7 sci data register (scixd) .............................................................................................20 1 11.3 functional description .................................................................................................... ..............201 11.3.1 baud rate ge neration .................................................................................................... .201 11.3.2 transmitter functiona l descriptio n ................................................................................202 11.3.3 receiver functiona l description ....................................................................................203 11.3.4 interrupts and st atus flags ............................................................................................. .205 11.3.5 additional sci f unctions ...............................................................................................2 06
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 15 section number title page chapter 12 serial peripheral interface (s08spiv3) 12.1 introducti on .............................................................................................................. .....................209 12.1.1 features ................................................................................................................ ...........211 12.1.2 block diagra ms .......................................................................................................... ....211 12.1.3 spi baud rate generation ..............................................................................................21 3 12.2 external signal de scription ............................................................................................... ...........214 12.2.1 spsck ? spi serial clock ............................................................................................214 12.2.2 mosi ? master data out, slave data in ......................................................................214 12.2.3 miso ? master data i n, slave data out ......................................................................214 12.2.4 ss ? slave select ..........................................................................................................214 12.3 modes of op eration ........................................................................................................ ...............215 12.3.1 spi in stop modes ....................................................................................................... ...215 12.4 register definition ....................................................................................................... .................215 12.4.1 spi control register 1 (spi1c1) ....................................................................................215 12.4.2 spi control register 2 (spi1c2) ....................................................................................216 12.4.3 spi baud rate register (spi1br) ..................................................................................217 12.4.4 spi status register (spi1s) ............................................................................................2 18 12.4.5 spi data register (spi1d) .............................................................................................21 9 12.5 functional description .................................................................................................... ..............220 12.5.1 spi clock fo rmats ....................................................................................................... ...220 12.5.2 spi interrupts .......................................................................................................... ........223 12.5.3 mode fault de tection .................................................................................................... .223 chapter 13 inter-integrated circuit (s08iicv2) 13.1 introducti on .............................................................................................................. .....................225 13.1.1 features ................................................................................................................ ...........227 13.1.2 modes of oper ation ...................................................................................................... ..227 13.1.3 block diag ram ........................................................................................................... .....227 13.2 external signal de scription ............................................................................................... ...........228 13.2.1 scl ? serial clock line ...............................................................................................22 8 13.2.2 sda ? serial data line ................................................................................................22 8 13.3 register definition ....................................................................................................... .................228 13.3.1 iic address register (iic1a) .........................................................................................229 13.3.2 iic frequency divider re gister (iic1f) ........................................................................229 13.3.3 iic control regist er (iic1c1) ........................................................................................232 13.3.4 iic status regist er (iic1s) ............................................................................................. 232 13.3.5 iic data i/o regist er (iic1d) ........................................................................................233 13.3.6 iic control register 2 (iic1c2) .....................................................................................234 13.4 functional description .................................................................................................... ..............235 13.4.1 iic protocol ............................................................................................................ .........235
mc9s08ac16 series data sheet, rev. 8 16 freescale semiconductor section number title page 13.4.2 10-bit address .......................................................................................................... .......238 13.4.3 general call address .................................................................................................... ..239 13.5 resets .................................................................................................................... ........................239 13.6 interrupts ................................................................................................................ .......................239 13.6.1 byte transfer interrupt ................................................................................................. ...239 13.6.2 address detect interrupt ................................................................................................ .240 13.6.3 arbitration lost interrupt .............................................................................................. ..240 13.7 initialization/applicat ion informat ion .................................................................................... ......241 chapter 14 analog-to-digital converter (s08adc10v1) 14.1 overview .................................................................................................................. .....................243 14.2 channel assignments ....................................................................................................... .............243 14.2.1 alternate clock ......................................................................................................... ......244 14.2.2 hardware trigger ........................................................................................................ ....244 14.2.3 temperature sensor ...................................................................................................... ..245 14.2.4 features ................................................................................................................ ...........247 14.2.5 block diag ram ........................................................................................................... .....247 14.3 external signal de scription ............................................................................................... ...........248 14.3.1 analog power (v ddad ) ..................................................................................................249 14.3.2 analog ground (v ssad ) .................................................................................................249 14.3.3 voltage reference high (v refh ) ...................................................................................249 14.3.4 voltage reference low (v refl ) ....................................................................................249 14.3.5 analog channel inputs (adx) ........................................................................................249 14.4 register definition ....................................................................................................... .................249 14.4.1 status and control regi ster 1 (adc1sc1) ....................................................................249 14.4.2 status and control regi ster 2 (adc1sc2) ....................................................................251 14.4.3 data result high regi ster (adc1rh) ...........................................................................252 14.4.4 data result low regi ster (adc1rl) ............................................................................252 14.4.5 compare value high register (adc1cvh) ..................................................................253 14.4.6 compare value low regi ster (adc1c vl) ...................................................................253 14.4.7 configuration regist er (adc1cfg) ..............................................................................253 14.4.8 pin control 1 regist er (apctl1) ..................................................................................255 14.4.9 pin control 2 regist er (apctl2) ..................................................................................256 14.4.10pin control 3 regist er (apctl3) ..................................................................................257 14.5 functional description .................................................................................................... ..............258 14.5.1 clock select and di vide control ....................................................................................258 14.5.2 input select and pin control ...........................................................................................2 59 14.5.3 hardware trigger ........................................................................................................ ....259 14.5.4 conversion c ontrol ...................................................................................................... ...259 14.5.5 automatic compare function .........................................................................................262 14.5.6 mcu wait mode op eration ............................................................................................262
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 17 section number title page 14.5.7 mcu stop3 mode operation ..........................................................................................262 14.5.8 mcu stop1 and stop2 mode operation .........................................................................263 14.6 initialization in formation ................................................................................................ ..............263 14.6.1 adc module initializa tion example .............................................................................263 14.7 application information ................................................................................................... .............265 14.7.1 external pins a nd routing ..............................................................................................2 65 14.7.2 sources of error ........................................................................................................ ......267 chapter 15 development support 15.1 introducti on .............................................................................................................. .....................271 15.1.1 features ................................................................................................................ ...........272 15.2 background debug contro ller (bdc) ......................................................................................... .272 15.2.1 bkgd pin descri ption ...................................................................................................2 73 15.2.2 communication de tails ..................................................................................................2 74 15.2.3 bdc commands ............................................................................................................ .278 15.2.4 bdc hardware br eakpoint .............................................................................................280 15.3 on-chip debug syst em (dbg) ................................................................................................ ....281 15.3.1 comparators a and b ..................................................................................................... 281 15.3.2 bus capture information a nd fifo operation ...............................................................281 15.3.3 change-of-flow in formation ..........................................................................................282 15.3.4 tag vs. force breakpoint s and triggers .........................................................................282 15.3.5 trigger modes ........................................................................................................... ......283 15.3.6 hardware breakpoints .................................................................................................... 285 15.4 register definition ....................................................................................................... .................285 15.4.1 bdc registers and control bits .....................................................................................285 15.4.2 system background debug force re set register (sbdfr) ..........................................287 15.4.3 dbg registers and c ontrol bits .....................................................................................288 appendix a electrical characteristics and timing specifications a.1 introducti on ................................................................................................................ ....................293 a.2 parameter clas sification.................................................................................................... .............293 a.3 absolute maximum ratings.................................................................................................... .......293 a.4 thermal charac teristic s..................................................................................................... .............294 a.5 esd protection and latch-up immunity .......................................................................................2 96 a.6 dc characteristics.......................................................................................................... ................297 a.7 supply current char acteristics.............................................................................................. .........301 a.8 adc characteristics......................................................................................................... ..............304 a.9 internal clock generation m odule characteristics ........................................................................307 a.9.1 icg frequency sp ecifications .........................................................................................308 a.10 ac characteristics......................................................................................................... .................311
mc9s08ac16 series data sheet, rev. 8 18 freescale semiconductor section number title page a.10.1 control ti ming ........................................................................................................... .....311 a.10.2 timer/pwm (tpm) module timing ...............................................................................312 a.11 spi charact eristics ........................................................................................................ .................314 a.12 flash specif ications....................................................................................................... .............316 a.13 emc performance............................................................................................................ ..............317 appendix b ordering information an d mechanical drawings b.1 ordering information ........................................................................................................ .............319 b.2 orderable part numbering system ............................................................................................. ...320 b.3 mechanical drawings......................................................................................................... ............321
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 19 chapter 1 introduction 1.1 overview the mc9s08ac16 series devices are members of the low-cost, high-perf ormance hcs08 family of 8-bit microcontroller units (mcus). all mcus in the fam ily use the enhanced hcs08 core and are available with a variety of modules, memory sizes, me mory types, and package types. refer to table 1-1 for memory sizes and package types. note ? the mc9s08ac16 and mc9s08ac8 devices are qualifi ed for, and are intended to be used in, consumer and industrial applications. ? the mc9s08aw16a and mc9s08aw8a devices are qualified for, and are intended to be used in, automotive applications. table 1-1 summarizes the feature set available in the mcus.
chapter 1 introduction mc9s08ac16 series data sheet, rev. 8 20 freescale semiconductor 1.2 mcu block diagrams the block diagram shows the struct ure of the mc9s08ac16 series mcu. table 1-1. features by mcu and package consumer and indust rial ?ac? devices feature mc9s08ac16 mc9s08ac8 flash size (bytes) 16k 8k ram size (bytes) 1024 768 pin quantity 48 44 42 32 48 44 42 32 adc channels 88868886 tpm1 channels 1 44444444 tpm2 channels 22222222 tpm3 channels 22222222 kbi pins 76647664 gpio pins 38 34 32 22 38 34 32 22 consumer & industrial qualified yes yes automotive qualified no no automotive ?aw? devices feature mc9s08aw16a mc9s08aw8a flash size (bytes) 16k 8k ram size (bytes) 1024 768 pin quantity 48 44 32 48 44 32 adc channels 8 8 6 8 8 6 tpm1 channels 1 1 there are 4 channels on tpm1 but two of them (tpm1ch2 and tpm1ch3) are not bonded to 32-pin lqfp package. these two channels can be used for soft timer function. 444444 tpm2 channels 2 2 2 2 2 2 tpm3 channels 2 2 2 2 2 2 kbi pins 764764 gpio pins 38 34 22 38 34 22 consumer & industrial qualified no no automotive qualified yes yes
chapter 1 introduction mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 21 figure 1-1. mc9s08ac16 block diagram ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
chapter 1 introduction mc9s08ac16 series data sheet, rev. 8 22 freescale semiconductor table 1-2 lists the functional versions of the on-chip modules. 1.3 system clock distribution figure 1-2. system clock distribution diagram some of the modules inside the mcu have clock source choices. figure 1-2 shows a simplified clock connection diagram. the icg supplies the clock sources: ? icgout is an output of the icg modul e. it is one of the following: ? the external crystal oscillator ? an external clock source ? the output of the digitally-controlled osci llator (dco) in the frequency-locked loop sub-module table 1-2. versions of on-chip modules module version analog-to-digital converter (adc) 1 internal clock generator (icg) 4 inter-integrated circuit (iic) 2 keyboard interrupt (kbi) 1 serial communications interface (sci) 4 serial peripheral interface (spi) 3 timer pulse-width modulator (tpm) 3 central processing unit (cpu) 2 tpm1 tpm2 iic1 sci1 sci2 spi1 bdc cpu adc1 ram flash icg icgout 32 ffe system logic busclk icglclk* control xclk** icgerclk * icglclk is the alternate bdc clock source for the mc9s08ac16 series. ** xclk is the fixed-frequency clock. 32 flash has frequency requirements for program and erase operation. see the electricals appendix. adc has min and max frequency requirements. see the electricals appendix and the adc chapter. tpm3 cop rti 1 khz tpmclk
chapter 1 introduction mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 23 ? control bits inside the icg dete rmine which source is connected. ? ffe is a control signal generated inside the icg. if the frequency of icgout > 4 the frequency of icgerclk, this signal is a logic 1 and th e fixed-frequency clock will be icgerclk/2. otherwise the fixed-frequenc y clock will be busclk. ? icglclk ? development tools can select this in ternal self-clocked source (~ 8 mhz) to speed up bdc communications in systems where the bus clock is slow. ? icgerclk ? external reference clock can be sele cted as the real-time interrupt clock source. can also be used as the altclk input to the adc module.
chapter 1 introduction mc9s08ac16 series data sheet, rev. 8 24 freescale semiconductor
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 25 chapter 2 pins and connections 2.1 introduction this chapter describes signals that connect to packag e pins. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 device pin assignment figure 2-1 shows the 48-pin qfn pin assignments for the mc9s08ac16 series device. figure 2-1. mc9s08ac16 series in 48-pin qfn package 37 ptf4/tpm2ch0 reset ptf0/tpm1ch2 ptg2/kbip2 ptg1/kbip1 ptg0/kbip0 v dd v ss pte7/spsck1 pte6/mosi1 ptd0/ad1p8 ptd1/ad1p9 v ddad v ssad ptb1/tpm3ch1/ad1p1 v refh ptc5/rxd2 ptg5/xtal bkgd/ms v refl ptg3/kbip3 ptf5/tpm2ch1 ptf6 pte0/txd1 pte3/tpm1ch1 pta0 pta1 pta2 ptb3/ad1p3 ptb2/ad1p2 ptg6/extal v ss ptc0/scl1 ptc1/sda1 ptf1/tpm1ch3 pte1/rxd1 pte2/tpm1ch0 ptd2/kbip5/ad1p10 ptd3/kbip6/ad1p11 ptc3/txd2 ptc2/mclk ptc4 irq/tpmclk pte4/ss1 pte5/miso1 ptb0/tpm3ch0/ad1p0 pta7 ptg4/kb1ip4 48-pin qfn 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 36 33 32 31 30 29 28 27 26 13 24 23 25 35 34 38 12
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 26 freescale semiconductor figure 2-2. shows the 44-pin lqfp pin assignmen ts for the mc9s08ac16 series device. figure 2-2. mc9s08ac16 series in 44-pin lqfp package ptf4/tpm2ch0 1 2 3 4 5 6 7 8 reset ptf0/tpm1ch2 ptg2/kbip2 ptg1/kbip1 ptg0/kbip0 v dd v ss pte7/spsck1 pte6/mosi1 ptd0/ad1p8 ptd1/ad1p9 v ddad v ssad ptb1/tpm3ch1/ad1p1 v refh ptc5/rxd2 ptg5/xtal bkgd/ms v refl ptg3/kbip3 31 30 29 28 27 26 13 14 15 16 17 18 34 35 12 22 23 33 44 9 ptf5/tpm2ch1 10 pte0/txd1 11 pte3/tpm1ch1 pta0 19 pta1 20 21 ptb3/ad1p3 ptb2/ad1p2 ptg6/extal 36 v ss 37 ptc0/scl1 38 ptc1/sda1 39 ptf1/tpm1ch3 pte1/rxd1 pte2/tpm1ch0 ptd2/kbip5/ad1p10 32 ptd3/kbip6/ad1p11 ptc3/txd2 43 42 41 ptc2/mclk 40 ptc4 irq/tpmclk pte4/ss1 pte5/miso1 ptb0/tpm3ch0/ad1p0 44-pin lqfp 25 24
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 27 figure 2-3 shows the 42-pin sdip pin assignments for the mc9s08ac16 series device. figure 2-3. mc9s08ac16 series in 42-pin sdip package 2 3 4 5 6 7 8 9 10 42-pin sdip 1 11 12 13 14 15 16 17 18 19 20 21 41 40 39 38 37 36 35 34 33 42 32 31 30 29 28 27 26 25 24 23 22 ptf4/tpm2ch0 reset ptf0/tpm1ch2 ptf5/tpm2ch1 pte0/txd1 pte3/tpm1ch1 ptf1/tpm1ch3 pte1/rxd1 pte2/tpm1ch0 irq/tpmclk ptc5/rxd2 ptc0/scl1 ptc1/sda1 ptc3/txd2 ptc2/mclk ptg2/kbip2 ptg1/kbip1 ptg0/kbip0 v dd v ss pte7/spsck1 pte6/mosi1 pta0 pte4/ss1 pte5/miso1 ptd0/ad1p8 ptd1/ad1p9 v ddad v ssad ptb1/tpm3ch1/ad1p1 ptg3/kbip3 ptb3/ad1p3 ptb2/ad1p2 ptd2/kbip5/ad1p10 ptd3/kbip6/ad1p11 ptb0/tpm3ch0/ad1p0 v refh ptg5/xtal bkgd/ms v refl ptg6/extal v ss
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 28 freescale semiconductor figure 2-4 shows the 32-pin lqfp pin assignmen ts for the mc9s08ac16 series device. figure 2-4. mc9s08ac16 series in 32-pin lqfp package ptf4/tpm2ch0 1 2 3 4 5 6 7 8 reset ptg1/kbip1 ptg0/kbip0 v dd v ss pte7/spsck1 pte6/mosi1 v ddad v ssad ptb1/tpm3ch1/ad1p1 v refh ptg5/xtal bkgd/ms v refl 22 21 20 19 18 17 10 11 12 13 14 15 9 24 32 ptf5/tpm2ch1 pte0/txd1 pte3/tpm1ch1 16 ptb3/ad1p3 ptb2/ad1p2 ptg6/extal v ss 25 ptc0/scl1 26 ptc1/sda1 27 pte1/rxd1 pte2/tpm1ch0 ptd2/ad1p10/kbip5 23 ptd3/ad1p11/kbip6 31 30 29 28 irq/tpmclk pte4/ss1 pte5/miso1 ptb0/tpm3ch0/ad1p0 32-pin lqfp
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 29 table 2-2. pin function reference signal function example(s) reference port pins ptax, ptbx chapter 6, ?parallel input/output ? serial peripheral interface ss , miso, mosi, spsck chapter 12, ?serial peripheral interface (s08spiv3) ? keyboard interrupts kbipx chapter 9, ?keyboard interrupt (s08kbiv1) ? timer/pwm tclk, tpmchx chapter 10, ?timer/pwm (s08tpmv3) ? inter-integrated circuit scl, sda chapter 13, ?inter-integrated circuit (s08iicv2) ? serial communications interface txd, rxd chapter 11, ?serial communications interface (s08sciv4) ? oscillator/clocking extal, xtal chapter 8, ?internal clock generator (s08icgv4) ? analog-to-digital adpx chapter 14, ?analog-to-digital converter (s08adc10v1) ? power/core bkgd/ms, v dd , v ss chapter 2, ?pins and connections ? reset and interrupts reset , irq chapter 5, ?resets, interrupts, and system configuration ? pin number <-- lowest priority --> highest 48 44 42 32 port pin alt 1 alt 2 11??ptc4 2261 irq tpmclk 3 3 7 2 reset 4 4 8 ? ptf0 tpm1ch2 5 5 9 ? ptf1 tpm1ch3 6 6 10 3 ptf4 tpm2ch0 7 7 11 4 ptf5 tpm2ch1 8???ptf6 9 8 12 5 pte0 txd1 10 9 13 6 pte1 rxd1 11 10 14 7 pte2 tpm1ch0 12 11 15 8 pte3 tpm1ch1 13 12 16 9 pte4 ss1 14 13 17 10 pte5 miso1 15 14 18 11 pte6 mosi1 16 15 19 12 pte7 spsck1 17 16 20 13 v ss 18 17 21 14 v dd 19 18 22 15 ptg0 kbip0 20 19 23 16 ptg1 kbip1 21 20 24 ? ptg2 kbip2 22 21 25 ? pta0 23 22 ? ? pta1 24 ? ? ? pta2 25 ? ? ? pta7 26 23 26 17 ptb0 tpm3ch0 ad1p0 27 24 27 18 ptb1 tpm3ch1 ad1p1 28 25 28 19 ptb2 ad1p2 29 26 29 20 ptb3 ad1p3 30 27 30 ? ptd0 ad1p8 31 28 31 ? ptd1 ad1p9 32 29 32 21 v ddad 33 30 33 22 v ssad 34 31 34 23 ptd2 ad1p10 kbip5 35 32 35 24 ptd3 ad1p11 kbip6 36 33 36 ? ptg3 kbip3 37 ? ? ? ptg4 kbip4 38 34 37 25 v refh 39 35 38 26 v refl 40 36 39 27 bkgd ms 41 37 40 28 ptg5 xtal 42 38 41 29 ptg6 extal 43 39 42 30 v ss 44 40 1 31 ptc0 scl1 45 41 2 32 ptc1 sda1 46 42 3 ? ptc2 mclk 47 43 4 ? ptc3 txd2 48 44 5 ? ptc5 rxd2 pin number <-- lowest priority --> highest 48 44 42 32 port pin alt 1 alt 2 table 2-1. pin availability by package pin-count
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 30 freescale semiconductor 2.3 recommended system connections figure 2-5 shows pin connections that are common to almost all mc9s08ac16 series application systems.
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 31 figure 2-5. basic system connections v dd v ss (x2) xtal extal bkgd/ms reset optional manual reset port a v dd background header c2 c1 x1 r f r s c by 0.1 f c blk 10 f + 5 v + system power i/o and peripheral interface to system application pta0 pta1 pta2 pta7 v dd port b ptb0/ad1p0/tpm3ch0 ptb1/ad1p1/tpm3ch1 ptb2/ad1p2 ptb3/ad1p3 port c ptc0/scl1 ptc1/sda1 ptc2/mclk ptc3/txd2 ptc4 ptc5/rxd2 port d ptd0/ad1p8 ptd1/ad1p9 ptd2/ad1p10/kbip5 ptd3/ad1p11/kbip6 port g ptg0/kbip0 ptg1/kbip1 ptg2/kbip2 ptg3/kbip3 ptg4/kbip4 port f ptf0/tpm1ch2 ptf1/tpm1ch3 ptf4/tpm2ch0 ptf5/tpm2ch1 ptf6 tpmclk/irq asynchronous interrupt input notes: 1. not required if using the internal clock option. 2. xtal and extal are ptg5 and ptg6 respectively. 3. rc filters on reset and irq are recommended for emc-sensitive applications. note 1 mc9s08ac16 v ddad v ssad c byad 0.1 f v refl v refh ptg5/xtal ptg6/extal note 2 note 2 v dd 4.7 k ? 0.1 f v dd 4.7 k ?10 k 0.1 f 10 k note 3 note 3 port e pte0/txd1 pte1/rxd1 pte2/tpm1ch0 pte3/tpm1ch1 pte4/ss 1 pte5/miso1 pte6/mosi1 pte7/spsck1
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 32 freescale semiconductor 2.3.1 power (v dd , 2 x v ss , v ddad , v ssad ) v dd and v ss are the primary power supply pi ns for the mcu. this voltage source supplies power to all i/o buffer circuitry and to an internal voltage regulator. the intern al voltage regulator provides regulated lower-voltage source to the cpu and ot her internal circuitry of the mcu. typically, application systems have two separate capac itors across the power pins. in this case, there should be a bulk electrolytic capacitor, such as a 10- f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1- f ceramic bypass capacitor located as near to the paired v dd and v ss power pins as practical to suppress high-frequency noise. the mc9s08ac16 has a second v ss pin. this pin should be connected to the syst em ground plane or to the primary v ss pin through a low-impedance connection. v ddad and v ssad are the analog power supply pi ns for the mcu. this volta ge source supplies power to the adc module. a 0.1- f ceramic bypass capacitor s hould be located as near to the analog power pins as practical to suppr ess high-frequency noise. 2.3.2 oscillator (xtal, extal) out of reset the mcu uses an internally generated clock (self-clocked mode ? f self_reset ) equivalent to about 8-mhz crystal rate. this fre quency source is used during reset startup and can be enabled as the clock source for stop r ecovery to avoid the need for a long crysta l startup delay. this mcu also contains a trimmable internal clock generator (icg) module that can be used to run the mcu. for more information on the icg, see the chapter 8, ?internal clock generator (s08icgv4) .? the oscillator in this mcu is a pierce oscillator th at can accommodate a crysta l or ceramic resonator in either of two frequency ranges selected by the range bi t in the icgc1 register. rather than a crystal or ceramic resonator, an external oscillator can be connected to the extal input pin. refer to figure 2-5 for the following discussion. r s (when used) and r f should be low-inductance resistors such as carbon composition resistors. wire-wound resi stors, and some metal film resistors, have too much inductance. c1 and c2 nor mally should be high-qual ity ceramic capacitors that are specifically designed for high-freque ncy applications. r f is used to provide a bias path to keep the extal input in its linear range during crysta l startup and its value is not generally crit ical. typical systems use 1 m to 10 m . higher values are sensitive to humidity and lower values re duce gain and (in extreme ca ses) could prevent startup. c1 and c2 are typically in the 5-pf to 25-pf range and are chosen to match the requirements of a specific crystal or resonator. be sure to take into acc ount printed circuit board (p cb) capacitance and mcu pin capacitance when sizing c1 and c2. the crystal manufacturer typical ly specifies a load capacitance which is the series combination of c1 and c2 which are usually the same size. as a first-order approximation, use 10 pf as an estimate of combined pin and p cb capacitance for each oscillator pin (extal and xtal). 2.3.3 reset reset is a dedicated pin with a pullup device built in. it has input hyste resis, a high current output driver, and no output slew rate control. in ternal power-on reset a nd low-voltage reset circ uitry typically make
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 33 external reset circuitry unnecessary . this pin is normally connected to the standard 6-pin background debug connector so a development syst em can directly reset the mcu system. if desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). whenever any reset is initiated (wheth er from an external signal or from an internal system), the reset pin is driven low for approximately 34 bus cycles. the re set circuitry decodes the cau se of reset and records it by setting a corresponding bit in the syst em control reset stat us register (srs). in emc-sensitive applications, an external rc filter is r ecommended on the reset pin. see figure 2-5 for an example. 2.3.4 background/mode select (bkgd/ms) while in reset, the bkgd/ms pin f unctions as a mode select pin. imme diately after reset rises the pin functions as the backgr ound pin and can be used for backgr ound debug communication. while functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. if nothing is connected to this pi n, the mcu will enter normal operating m ode at the rising edge of reset. if a debug system is connected to the 6-pin standard background de bug header, it can hold bkgd/ms low during the rising edge of reset which fo rces the mcu to active background mode. the bkgd pin is used primarily for background debug controller (bdc) communi cations using a custom protocol that uses 16 clock cycles of the target mcu?s bdc clock per bit time. the target mcu?s bdc clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the bkgd/ms pin that could interfer e with background serial communications. although the bkgd pin is a ps eudo open-drain pin, the backgr ound debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise time s. small capacitances from cables and the absolute valu e of the internal pullup devi ce play almost no role in determining rise and fall times on the bkgd pin. 2.3.5 adc reference pins (v refh , v refl ) the v refh and v refl pins are the voltage reference high and voltage reference low inputs respectively for the adc module. 2.3.6 external interrupt pin (irq) the irq pin is the input source for the irq interrupt a nd is also the input for th e bih and bil instructions. if the irq function is not enabled, th is pin does not perform any function. in emc-sensitive applications, an external rc filter is recommended on the irq pin. see figure 2-5 for an example.
chapter 2 pins and connections mc9s08ac16 series data sheet, rev. 8 34 freescale semiconductor 2.3.7 general-purpose i/o and peripheral ports the remaining pins are shared among general-purpose i/o and on- chip peripheral functi ons such as timers and serial i/o systems. immediately after reset, al l of these pins are conf igured as high-impedance general-purpose inputs with inte rnal pullup devices disabled. note to avoid extra current drain from floa ting input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the dire ction of unused pins to outputs so the pins do not float. for information about controlling these pins as general-pur pose i/o pins, see chapter 6, ?parallel input/output .? for information about how and when on-chip peripheral systems use these pins, refer to the appropriate chapter from table 2-2 . when an on-chip peripheral system is controlling a pin, data direction c ontrol bits still determine what is read from port data registers even though the periphe ral module controls the pi n direction by controlling the enable for the pin?s output buffer. see the chapter 6, ?parallel input/output ? chapter for more details. pullup enable bits for each input pin control whether on-ch ip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip pe ripheral module. when the ptd3, ptd2, and ptg4 pins are controlled by the kbi module and are configured for rising-e dge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. similarly, when irq is configured as the irq input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. note when an alternative function is first en abled it is possible to get a spurious edge to the module, user software sh ould clear out any associated flags before interrupts are enabled. table 2-1 illustrates the priority if multiple modules are enabled. the highest priori ty module will have control over the pin. selecting a higher priority pin f unction with a lower priority function already enabled can cause s purious edges to the lower priority module. it is recommended that all modul es that share a pin be disabled before enabling another module.
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 35 chapter 3 modes of operation 3.1 introduction the operating modes of the mc9s08ac16 series are described in this chap ter. entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 features ? active background mode for code development ? wait mode: ? cpu shuts down to conserve power ? system clocks running ? full voltage regulation maintained ? stop modes: ? system clocks stopped; vol tage regulator in standby ? stop2 ? partial power down of intern al circuits, ram contents retained ? stop3 ? all internal circuits powered for fast recovery 3.3 run mode this is the normal operating mode for the mc9s08a c16 series. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode , the cpu executes code from internal memory with execution beginning at the address fe tched from memory at 0xfffe:0xffff after reset. 3.4 active background mode the active background mode functions are manage d through the background de bug controller (bdc) in the hcs08 core. the bdc, together with the on- chip debug module (dbg), provide the means for analyzing mcu operation duri ng software development. active background mode is en tered in any of five ways: ? when the bkgd/ms pin is low at the rising edge of reset ? when a background command is received through the bkgd pin ? when a bgnd instruction is executed ? when encountering a bdc breakpoint ? when encountering a dbg breakpoint
chapter 3 modes of operation mc9s08ac16 series data sheet, rev. 8 36 freescale semiconductor after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructi ons from the user?s application program. background commands are of two types: ? non-intrusive commands, defined as commands that can be issu ed while the user program is running. non-intrusive commands can be issued through the bkgd pin while the mcu is in run mode; non-intrusive commands ca n also be executed when the mcu is in the active background mode. non-intrusive commands include: ? memory access commands ? memory-access-with-status commands ? bdc register access commands ? the background command ? active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: ? read or write cpu registers ? trace one user program instruction at a time ? leave active background mode to return to the user?s application program (go) the active background mode is used to program a bootloader or user a pplication program into the flash program memory before the mcu is operated in r un mode for the first time. when the mc9s08ac16 series is shipped from the freescal e semiconductor factory, the flas h program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the flash memory is initially program med. the active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about th e active background mode, refer to chapter 15, ?development support .? 3.5 wait mode wait mode is entered by executing a wait instruction. u pon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking opera tions leading to the in terrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background co mmand and memory-access-with-s tatus commands are available when the mcu is in wait mode. the memory-access- with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode. 3.6 stop modes one of two stop modes is entered upon execution of a st op instruction when the stope bit in the system option register is set. in both stop modes, all internal clocks are halte d. if the stope bit is not set when
chapter 3 modes of operation mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 37 the cpu executes a stop instruction, the mcu will not enter either of the stop modes and an illegal opcode reset is forced. the stop modes are sel ected by setting the appropriate bits in spmsc2. hcs08 devices that are designed for low voltage ope ration (1.8v to 3.6v) also include stop1 mode. the mc9s08ac16 series family of de vices does not include stop1 mode. table 3-1 summarizes the behavior of th e mcu in each of the stop modes. 3.6.1 stop2 mode the stop2 mode provides very low standby power cons umption and maintains the contents of ram and the current state of all of the i/o pins. to enter st op2, the user must execute a stop instruction with stop2 selected (ppdc = 1) and stop mode enabled (stope = 1). in addition, the lvd must not be enabled to operate in stop (lvdse = lvde = 1). if the lvd is enabled in stop, then the mcu enters stop3 upon the execution of the stop instruction re gardless of the state of ppdc. before entering stop2 mode, the user must save the conten ts of the i/o port registers, as well as any other memory-mapped registers which they want to restore after exit of st op2, to locations in ram. upon exit of stop2, these values can be restored by user software before pin latches are opened. when the mcu is in stop2 mode, all internal circuits th at are powered from the vol tage regulator are turned off, except for the ram. the voltage regulator is in a low-power standby state, as is the adc. upon entry into stop2, the states of the i/o pins are latched. the st ates are held while in st op2 mode and after exiting stop2 mode until a logic 1 is written to ppdack in spmsc2. exit from stop2 is done by asserting either of the wake-up pins: reset or irq/tpmclk, or by an rti interrupt. irq/tpmclk is always an active low input when the mcu is in stop2, regardless of how it was configured before entering stop2. upon wake-up from stop2 mode, the mcu will start up as from a power-on reset (por) except pin states remain latched. the cpu will take the reset vector. the system and all peripherals will be in their default reset states and must be initialized. after waking up from stop2, the ppdf bit in spmsc2 is set. this flag may be used to direct user code to go to a stop2 recovery routine. ppdf remains set and th e i/o pin states remain la tched until a logic 1 is written to ppdack in spmsc2. to maintain i/o state for pins that were configured as general-purpose i/o, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restor ed from ram before writing to ppdack, then the table 3-1. stop mode behavior mode ppdc cpu, digital peripherals, flash ram icg adc regulator i/o pins rti stop2 1 off standby off disabled standby states held optionally on stop3 0 standby standby off 1 1 crystal oscillator can be configured to r un in stop3. please see the icg registers. optionally on standby states held optionally on
chapter 3 modes of operation mc9s08ac16 series data sheet, rev. 8 38 freescale semiconductor register bits will assume their rese t states when the i/o pin latches are opened and the i/o pins will switch to their reset states. for pins that were configured as peripheral i/o, the user must reconfigure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.2 stop3 mode to enter stop3, the user must execute a stop instru ction with stop3 selected (ppdc = 0) and stop mode enabled (stope = 1). upon entering th e stop3 mode, all of the clocks in the mcu, including the oscillator itself, are halted. the icg enters its standby state, as does the voltage regulator and the adc. the states of all of the internal registers and logic, as well as the ram content, are maintained. the i/o pin states are not latched at the pin as in stop2. instead they are main tained by virtue of the stat es of the internal logic driving the pins being maintained. exit from stop3 is done by asserting reset or by an interrupt from one of the following sources: the real-time interrupt (rti), lvd system, adc, irq, kbi, or sci. if stop3 is exited by means of the reset pin, then the mcu will be rese t and operation will resume after taking the reset vector. exit by means of an asynchronous interrupt or the real-time interrupt will result in the mcu taking the appropriate interrupt vector. a separate self-clocked source ( 1 khz) for the real-time interrupt a llows a wakeup from stop2 or stop3 mode with no external components. when rtis2:rt is1:rtis0 = 0:0:0, the real -time interrupt function and this 1-khz source are disabled. po wer consumption is lower when the 1-khz source is disabled, but in that case the real-time interrupt cannot wake the mcu from stop. 3.6.3 active bdm enabled in stop mode entry into the active bac kground mode from run mode is enabled if the enbdm bit in bdcscr is set. this register is described in chapter 15, ?development support ? of this data sheet. if enbdm is set when the cpu executes a stop instruction, the system clocks to the background de bug logic remain active when the mcu enters stop mode so background debug communication is still possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. if the user attempts to enter st op2 with enbdm set, the mc u will instead enter stop3. most background commands are not available in stop mode. the memo ry-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. af ter entering background de bug mode, all background commands are available. table 3-2 summarizes the behavior of the mcu in stop when entry into the background debug mode is enabled.
chapter 3 modes of operation mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 39 3.6.4 lvd enabled in stop mode the lvd system is capable of genera ting either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enabled in stop by sett ing the lvde and the lvdse bits, then the voltage regulator remains active during stop m ode. if the user attempts to enter stop2 with the lvd enabled for stop, the mcu will instead enter stop3. table 3-3 summarizes the behavior of the mcu in stop when the lvd is enabled. 3.6.5 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal periphera l modules are stopped. even in the exception case (enbdm = 1), where clocks are kept alive to the background debug logic, clocks to the peripheral systems are halted to reduce power consumption. refer to section 3.6.2, ?stop3 mode ? for specific information on system behavior in stop modes. i/o pins ? all i/o pin states remain unchange d when the mcu enters stop3 mode. ? if the mcu is configured to go into stop2 mode, all i/o pins states are latched before entering stop. memory ? all ram and register contents are pr eserved while the mcu is in stop3 mode. ? all registers will be reset up on wake-up from stop2, but the contents of ram are preserved and pin states remain latched until the ppdack bit is written. the user may save any memory-mapped register data into ram before entering sto p2 and restore the data upon exit from stop2. ? the contents of the flash memory are non-volat ile and are preserved in any of the stop modes. icg ? in stop3 mode, the icg enters its low-power st andby state. the oscillator may be kept running when the icg is in standby by setting oscsten. in st op2 mode, the icg is turned off. the oscillator cannot be kept running in stop2 even if oscsten is set. if the mcu is configured to go into stop2 mode, the icg will be reset upon wake-up fr om stop and must be reinitialized. table 3-2. bdm enabled stop mode behavior mode ppdc cpu, digital peripherals, flash ram icg adc regulator i/o pins rti stop3 0 standby standby active optionally on active states held optionally on table 3-3. lvd enabled stop mode behavior mode ppdc cpu, digital peripherals, flash ram icg adc regulator i/o pins rti stop3 0 standby standby off optionally on active states held optionally on
chapter 3 modes of operation mc9s08ac16 series data sheet, rev. 8 40 freescale semiconductor tpm ? when the mcu enters stop mode, the clock to the tpm1 and tpm2 modules stop. the modules halt operation. if the mcu is configured to go in to stop2 mode, the tpm modules will be reset upon wake-up from stop and must be reinitialized. adc ? when the mcu enters stop mode, the adc wi ll enter a low-power standby state unless the asynchronous clock source, adack, is enabled. conversions can occur in stop3 if adack is enabled. if the mcu is configured to go into stop2 mode, th e adc will be reset upon wake-up from stop and must be re-initialized. kbi ? during stop3, the kbi pins that are enabled cont inue to function as inte rrupt sources that are capable of waking the mcu from stop3. the kbi is di sabled in stop2 and must be reinitialized after waking up. sci ? when the mcu enters stop mode, the clocks to the sci1 and sci2 modules stop. the modules halt operation. if the mcu is configured to go in to stop2 mode, the sci modules will be reset upon wake-up from stop and must be reinitialized. spi ? when the mcu enters stop m ode, the clocks to the spi modul e stop. the module halts operation. if the mcu is configured to go in to stop2 mode, the spi module will be reset upon wake-up from stop and must be reinitialized. iic ? when the mcu enters stop mo de, the clocks to the iic modul e stops. the modul e halts operation. if the mcu is configured to go in to stop2 mode, the iic module will be reset upon wake-up from stop and must be reinitialized. voltage regulator ? the voltage regulator ente rs a low-power standby state wh en the mcu enters either of the stop modes unless the lvd is enab led in stop mode or bdm is enabled.
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 41 chapter 4 memory 4.1 mc9s08ac16 series memory map figure 4-1 shows the memory maps for the mc9s08ac 16 series mcus. on-chip memory in the mc9s08ac16 series of mcu consis ts of ram, flash program memory for nonvolatile data storage, plus i/o and control/status registers. the registers ar e divided into three groups: ? direct-page registers (0x0000 through 0x006f) ? high-page registers (0x1800 through 0x185f) ? nonvolatile registers (0xffb0 through 0xffbf) figure 4-1. mc9s08ac16 series memory maps mc9s08ac16 and mc9s08aw16a direct page registers ram unimplemented high page registers 1024 bytes 5008 bytes 0x0000 0x006f 0x0070 0x046f 0x1800 0x17ff 0x185f 0xffff 0x0470 flash 16,384 bytes 0x1860 unimplemented 42,912 bytes 0xbfff 0xc000 mc9s08ac8 and mc9s08aw8a direct page registers ram unimplemented high page registers 768 bytes 5008 bytes 0x0000 0x006f 0x0070 0x1800 0x17ff 0x185f 0xffff flash 8192 bytes 0x1860 0xdfff 0xe000 reserved ? 256 bytes 0x046f 0x0470 0x036f 0x0370 unimplemented 42,912 bytes 0xbfff 0xc000 reserved 8192 bytes
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 42 freescale semiconductor 4.1.1 reset and interrupt vector assignments figure 4-1 shows address assignments for re set and interrupt vector s. the vector names shown in this table are the labels used in the freesca le-provided equate file for the mc 9s08ac16 series. for more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to chapter 5, ?resets, interrupts, and system configuration .? table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:ffc1 through 0xffc4 :ffc5 unused vector space (available for user program) ? 0xffc6:ffc7 tpm3 overflow vtpm3ovf 0xffc8:ffc9 tpm3 channel 1 vtpm3ch1 0xffca:ffcb tpm3 channel 0 vtpm3ch0 0xffcc:ffcd rti vrti 0xffce:ffcf iic1 viic1 0xffd0:ffd1 adc1 conversion vadc1 0xffd2:ffd3 kbi vkeyboard1 0xffd4:ffd5 sci2 transmit vsci2tx 0xffd6:ffd7 sci2 receive vsci2rx 0xffd8:ffd9 sci2 error vsci2err 0xffda:ffdb sci1 transmit vsci1tx 0xffdc:ffdd sci1 receive vsci1rx 0xffde:ffdf sci1 error vsci1err 0xffe0:ffe1 spi1 vspi1 0xffe2:ffe3 tpm2 overflow vtpm2ovf 0xffe4:ffe5 tpm2 channel 1 vtpm2ch1 0xffe6:ffe7 tpm2 channel 0 vtpm2ch0 0xffe8:ffe9 tpm1 overflow vtpm1ovf 0xffea:ffeb unused ? 0xffec:ffed unused ? 0xffee:ffef tpm1 channel 3 vtpm1ch3 0xfff0:fff1 tpm1 channel 2 vtpm1ch2 0xfff2:fff3 tpm1 channel 1 vtpm1ch1 0xfff4:fff5 tpm1 channel 0 vtpm1ch0 0xfff6:fff7 icg vicg 0xfff8:fff9 low voltage detect vlvd 0xfffa:fffb irq virq 0xfffc:fffd swi vswi 0xfffe:ffff reset vreset
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 43 4.2 register addresses and bit assignments the registers in the mc9s08ac16 series are divided into these three groups: ? direct-page registers are located in the first 112 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. ? high-page registers are used much less ofte n, so they are located above 0x1800 in the memory map. this leaves more room in the direct page fo r more frequently used registers and variables. ? the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?0xffbf. nonvolatile register locations include: ? three values which are loaded in to working registers at reset ? an 8-byte backdoor comparison key which optionall y allows a user to gain controlled access to secure memory because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with efficient direct addressing mode inst ructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page re gisters and control bits. the direct page registers in table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. because of th is, the lower byte of the address in column one is shown in bold text. in table 4-3 and table 4-4 the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the ri ght. cells that are not associated with na med bits are shaded. a shaded cell with a 0 indicates this unused bi t always reads as a 0. shad ed cells with dashes indi cate unused or reserved bit locations that could read as 1s or 0s.
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 44 freescale semiconductor table 4-2. direct-page register summary (sheet 1 of 3) addressregister namebit 7654321bit 0 0x00 00 ptad ptad7 r r r r ptad2 ptad1 ptad0 0x00 01 ptadd ptadd7 r r r r ptadd2 ptadd1 ptadd0 0x00 02 ptbd r r r r ptbd3 ptbd2 ptbd1 ptbd0 0x00 03 ptbdd r r r r ptbdd3 ptbdd2 ptbdd1 ptbdd0 0x00 04 ptcd 0 r ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 0x00 05 ptcdd 0 r ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 0x00 06 ptdd r r r r ptdd3 ptdd2 ptdd1 ptdd0 0x00 07 ptddd r r r r ptddd3 ptddd2 ptddd1 ptddd0 0x00 08 pted pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 0x00 09 ptedd ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 0x00 0a ptfd r ptfd6 ptfd5 ptfd4 r rptfd1ptfd0 0x00 0b ptfdd r ptfdd6 ptfdd5 ptfdd4 r r ptfdd1 ptfdd0 0x00 0c ptgd 0 ptgd6 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 0x00 0d ptgdd 0 ptgdd6 ptgdd5 ptgdd4 ptgd d3 ptgdd2 ptgdd1 ptgdd0 0x00 0e ? 0x00 0f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 10 adc1sc1 coco aien adco adch 0x00 11 adc1sc2 adact adtrg acfe acfgt 0 0 r r 0x00 12 adc1rh 0 0 0 0 0 0 adr9 adr8 0x00 13 adc1rl adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0x00 14 adc1cvh 0 0 0 0 0 0 adcv9 adcv8 0x00 15 adc1cvl adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 0x00 16 adc1cfg adlpc adiv adlsmp mode adiclk 0x00 17 apctl1 adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 0x00 18 apctl2 adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 0x00 19 apctl3 adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 0x00 1a ? 0x00 1b reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 1c irqsc 0 irqpdd irqedg irqpe irqf irqack irqie irqmod 0x00 1d reserved ? ? ? ? ? ? ? ? 0x00 1e kbisc 0 kbedg6 kbedg5 kbedg4 kbf kback kbie kbimod 0x00 1f kbipe 0 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 0x00 20 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 21 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 0x00 22 tpm1cntl bit 7654321bit 0 0x00 23 tpm1modh bit 15 14 13 12 11 10 9 bit 8 0x00 24 tpm1modl bit 7654321bit 0 0x00 25 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 26 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 27 tpm1c0vl bit 7654321bit 0
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 45 0x00 28 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 29 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 2a tpm1c1vl bit 7654321bit 0 0x00 2b tpm1c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 0x00 2c tpm1c2vh bit 15 14 13 12 11 10 9 bit 8 0x00 2d tpm1c2vl bit 7654321bit 0 0x00 2e tpm1c3sc ch3f ch3ie ms3b ms3a els3b els3a 0 0 0x00 2f tpm1c3vh bit 15 14 13 12 11 10 9 bit 8 0x00 30 tpm1c3vl bit 7654321bit 0 0x00 31 ? 0x00 37 reserved ? ? ? ? ? ? ? ? 0x00 38 sci1bdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 39 sci1bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 3a sci1c1 loops sciswai rsrc m wake ilt pe pt 0x00 3b sci1c2 tie tcie rie ilie te re rwu sbk 0x00 3c sci1s1 tdre tc rdrf idle or nf fe pf 0x00 3d sci1s2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 3e sci1c3 r8 t8 txdir txinv orie neie feie peie 0x00 3f sci1d bit 7654321bit 0 0x00 40 sci2bdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 41 sci2bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 42 sci2c1 loops sciswai rsrc m wake ilt pe pt 0x00 43 sci2c2 tie tcie rie ilie te re rwu sbk 0x00 44 sci2s1 tdre tc rdrf idle or nf fe pf 0x00 45 sci2s2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 46 sci2c3 r8 t8 txdir txinv orie neie feie peie 0x00 47 sci2d bit 7654321bit 0 0x00 48 icgc1 hgo range refs clks oscsten locd 0 0x00 49 icgc2 lolre mfd locre rfd 0x00 4a icgs1 clkst refst lols lock locs ercs icgif 0x00 4b icgs2 0 0 0 0 0 0 0 dcos 0x00 4c icgfltu 0 0 0 0flt 0x00 4d icgfltl flt 0x00 4e icgtrm trim 0x00 4f reserved ? ? ? ? ? ? ? ? 0x00 50 spi1c1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 51 spi1c2 0 0 0 modfen bidiroe 0 spiswai spc0 0x00 52 spi1br 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 53 spi1s sprf 0 sptef modf 0 0 0 0 0x00 54 spi1d bit 7654321bit 0 table 4-2. direct-page register summary (sheet 2 of 3) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 46 freescale semiconductor high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the dire ct addressable memory space, starting at 0x1800. 0x00 55 ? 0x00 57 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 58 iic1a ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 0x00 59 iic1f mult icr 0x00 5a iic1c1 iicen iicie mst tx txak rsta 0 0 0x00 5b iic1s tcf iaas busy arbl 0 srw iicif rxak 0x00 5c iic1d data 0x00 5d iic1c2 gcaen adext 0 0 0 ad10 ad9 ad8 0x00 5e ? 0x00 5f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 62 tpm2cntl bit 7654321bit 0 0x00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 64 tpm2modl bit 7654321bit 0 0x00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 67 tpm2c0vl bit 7654321bit 0 0x00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 6a tpm2c1vl bit 7654321bit 0 0x00 6b ? 0x00 6f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 4-3. high-page register summary (sheet 1 of 3) addressregister namebit 7654321bit 0 0x1800 srs por pin cop ilop ilad icg lvd 0 0x1801 sbdfr 0 0 0 0 0 0 0bdfr 0x1802 sopt cope copt stope ? 0 0 ? ? 0x1803 smclk 0 0 0mpe 0 mcsel 0x1804 ? 0x1805 reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1806 sdidh rev3 rev2 rev1 rev0 id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 srtisc rtif rtiack rticlks rtie 0 rtis2 rtis1 rtis0 0x1809 spmsc1 lvdf lvdack lvdie lvdre lvdse lvde 0 1 bgbe 0x180a spmsc2 lv w f lv wac k lv dv lv w v p p d f p p dac k ? ppdc 0x180b reserved ? ? ? ? ? ? ? ? table 4-2. direct-page register summary (sheet 3 of 3) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 47 0x180c sopt2 copclks ? ? ? ? ? ? ? 0x180d? 0x180f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 0x1811 dbgcal bit 7654321bit 0 0x1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 0x1813 dbgcbl bit 7654321bit 0 0x1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 0x1815 dbgfl bit 7654321bit 0 0x1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben 0x1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 0x1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 0x1819 ? 0x181f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1820 fcdiv divld prdiv8 div5 div4 div3 div2 div1 div0 0x1821 fopt keyen fnored 0 0 0 0 sec01 sec00 0x1822 reserved ? ? ? ? ? ? ? ? 0x1823 fcnfg 0 0 keyacc 0 0 0 0 0 0x1824 fprot fps7 fps6 fps5 fps4 f ps3 fps2 fps1 fpdis 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 0x1827 ? 0x182f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1830 tpm3sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x1831 tpm3cnth bit 15 14 13 12 11 10 9 bit 8 0x1832 tpm3cntl bit 7654321bit 0 0x1833 tpm3modh bit 15 14 13 12 11 10 9 bit 8 0x1834 tpm3modl bit 7654321bit 0 0x1835 tpm3c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x1836 tpm3c0vh bit 15 14 13 12 11 10 9 bit 8 0x1837 tpm3c0vl bit 7654321bit 0 0x1838 tpm3c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x1839 tpm3c1vh bit 15 14 13 12 11 10 9 bit 8 0x183a tpm3c1vl bit 7654321bit 0 0x183b 0x183f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x1840 ptape ptape7 r r r r ptape2 ptape1 ptape0 0x1841 ptase ptase7 r r r r ptase2 ptase1 ptase0 0x1842 ptads ptads7 r r r r p ta d s 2 p ta d s 1 p ta d s 0 0x1843 reserved ? ? ? ? ? ? ? ? table 4-3. high-page register summary (sheet 2 of 3) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 48 freescale semiconductor nonvolatile flash registers, shown in table 4-4 , are located in the flash memory. these registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. during reset events, the contents of nvprot and n vopt in the nonvolatile regi ster area of the flash memory are transferred into corr esponding fprot and fopt working regi sters in the high-page registers to control security and block protection options. 0x1844 ptbpe r r r r ptbpe3 ptbpe2 ptbpe1 ptbpe0 0x1845 ptbse r r r r ptbse3 ptbse2 ptbse1 ptbse0 0x1846 ptbds r r r r ptbds3 ptbds2 ptbds1 ptbds0 0x1847 reserved ? ? ? ? ? ? ? ? 0x1848 ptcpe 0 r ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 0x1849 ptcse 0 r ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 0x184a ptcds 0 r ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 0x184b reserved ? ? ? ? ? ? ? ? 0x184c ptdpe r r r r ptdpe3 ptdpe2 ptdpe1 ptdpe0 0x184d ptdse r r r r ptdse3 ptdse2 ptdse1 ptdse0 0x184e ptdds r r r r ptdds3 ptdds2 ptdds1 ptdds0 0x184f reserved ? ? ? ? ? ? ? ? 0x1850 ptepe ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 0x1851 ptese ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 0x1852 pteds pteds7 pteds6 pteds5 pteds4 pteds3 pteds2 pteds1 pteds0 0x1853 reserved ? ? ? ? ? ? ? ? 0x1854 ptfpe r ptfpe6 ptfpe5 ptfpe4 r r ptfpe1 ptfpe0 0x1855 ptfse r ptfse6 ptfse5 ptfse4 r r ptfse1 ptfse0 0x1856 ptfds r ptfds6 ptfds5 ptfds4 r r ptfds1 ptfds0 0x1857 reserved ? ? ? ? ? ? ? ? 0x1858 ptgpe 0 ptgpe6 ptgpe5 ptgpe4 ptg pe3 ptgpe2 ptgpe1 ptgpe0 0x1859 ptgse 0 ptgse6 ptgse5 ptgse4 ptg se3 ptgse2 ptgse1 ptgse0 0x185a ptgds 0 ptgds6 ptgds5 ptgds4 ptgds3 ptgds2 ptgds1 ptgds0 0x185b? 0x185f reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 this reserved bit must always be written to 0. table 4-3. high-page register summary (sheet 3 of 3) addressregister namebit 7654321bit 0
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 49 provided the key enable (keyen) bit is 1, the 8-by te comparison key can be used to temporarily disengage memory security. this ke y mechanism can be accessed only th rough user code running in secure memory. (a security key cannot be entere d directly through ba ckground debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if th e security key is disabled, the only way to disengage security is by mass erasing th e flash if needed (norma lly through the background debug interface) and verifying that flas h is blank. to avoid returning to s ecure mode after the next reset, program the security bits (sec01:se c00) to the unsecured state (1:0). 4.3 ram the mc9s08ac16 series includes static ram. the locations in ram below 0x0100 can be accessed using the more efficient direct addr essing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low- power wait, stop2, or st op3 mode. at power-on, the contents of ram are uninitialized. ram data is unaffected by any rese t provided that the supply voltage does not drop below the minimum value for ram retention. for compatibility with older m68hc05 mcus, the hc s08 resets the stack pointer to 0x00ff. in the mc9s08ac16 series, it is usua lly best to re-initialize the stack pointer to the top of the ram so the direct page ram can be used for frequently accessed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your re set initialization routine (w here ramlast is equated to the highest address of the ram in the freescale-provided equate file). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) table 4-4. nonvolatile register summary addressregister namebit 7654321bit 0 0xffb0 ? 0xffb7 nvbackkey 8-byte comparison key 0xffb8 ? 0xffbb reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xffbc reserved for stor- age of 250 khz icgtrm value ? ? ? ? ? ? ? ? 0xffbd nvprot fps7 fps6 fps5 fps4 f ps3 fps2 fps1 fpdis 0xffbe reserved for stor- age of 243 khz icgtrm value ? ? ? ? ? ? ? ? 0xffbf nvopt keyen fnored 0 0 0 0 sec01 sec00
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 50 freescale semiconductor when security is enabled, the ram is considered a secure memory resource a nd is not accessible through bdm or through code executing from non-secure memory. see section 4.5, ?security ? for a detailed description of the security feature. 4.4 flash the flash memory is intended primarily for progr am storage. in-circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product. it is possible to program the entire array through the single-wire background de bug interface. because no special voltages are needed for flash erase a nd programming operations, in -application programming is also possible through other softwa re-controlled communication paths. for a more detaile d discussion of in-circuit and in-applicati on programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor documen t order number hcs08rmv1/d. 4.4.1 features features of the flash memory include: ?flash size ? mc9s08ac16 and mc9s08aw16a? 16,384 byt es (32 pages of 512 bytes each) ? mc9s08ac8 and mc9s08aw8a? 8192 bytes (16 pages of 512 bytes each) ? single power supply program and erase ? command interface for fast program and erase operation ? up to 100,000 program/erase cycles at typical voltage and temperature ? flexible block protection ? security feature for flash and ram ? auto power-down for low-frequency read accesses 4.4.2 program and erase times before any program or erase command can be accepte d, the flash clock divide r register (fcdiv) must be written to set the internal cloc k for the flash module to a frequency (f fclk ) between 150 khz and 200 khz (see section 4.6.1, ?flash clock di vider register (fcdiv) ?). this register can be written only once, so normally this write is done during reset init ialization. fcdiv cannot be wr itten if the access error flag, faccerr in fstat, is set. the user must ensu re that faccerr is not set before writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program and erase pulses. an integer number of th ese timing pulses are used by the command processor to complete a program or erase command. table 4-5 shows program and erase times . the bus clock fre quency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk =1/f fclk . the times are shown as a number of cycles of fclk and as an ab solute time for the case where t fclk =5 s. program and erase times shown include overhead for the command state machin e and enabling and disablin g of program and erase voltages.
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 51 4.4.3 program and erase command execution the steps for executing any of the co mmands are listed below. the fcdiv register must be initialized and any error flags cleared before beginning comma nd execution. the command execution steps are: 1. write a data value to an address in the flash array. the address and data information from this write is latched into the flash interface. this write is a required first step in any command sequence. for erase and blank check commands, the value of the data is not important. for page erase commands, the address may be any address in the 512-byte page of flash to be erased. for mass erase and blank check commands, the addre ss can be any address in the flash memory. whole pages of 512 bytes are the sm allest block of flash that may be erased. in the 60k version, there are two instances where the si ze of a block that is accessible to the user is less than 512 bytes: the first page following ram, and the first page following the high page re gisters. these pages are overlapped by the ram and high page registers respectively. note do not program any byte in the flash more than once after a successful erase operation. reprogr amming bits to a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entir e flash memory. programming without first erasing may disturb da ta stored in the flash. 2. write the command code for the desired command to fcmd. the five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launc hes the complete command. aborting a command in this way sets the faccerr acc ess error flag which must be cleared before starting a new command. a strictly monitored procedure must be obeyed or the command will not be accepted. this minimizes the possibility of any unintended cha nges to the flash memory contents. the command complete flag (fccf) indicates when a command is complete. th e command sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a flowchart for executing all of the commands except for table 4-5. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s byte program (burst) 4 20 s 1 1 excluding start/end overhead page erase 4000 20 ms mass erase 20,000 100 ms
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 52 freescale semiconductor burst programming. the fcdiv register must be initialized before using any flash commands. this only must be done once following a reset. figure 4-2. flash program and erase flowchart 4.4.4 burst program execution the burst program command is used to program sequential bytes of da ta in less time than would be required using the standard program command. this is possible becaus e the high voltage to the flash array does not need to be disabled between progra m operations. ordinarily, when a program or erase command is issued, an internal ch arge pump associated with the fl ash memory must be enabled to supply high voltage to the array. u pon completion of the command, the ch arge pump is turned off. when a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met: ? the next burst program command has been que ued before the current program operation has completed. start write to flash to buffer address and data write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef (note 2) 1 0 fccf ? error exit done note 2: wait at least four bus cycles 0 faccerr ? clear error faccerr ? write to fcdiv (note 1) note 1: required only once after reset. 1 before checking fcbef or fccf. flash program and erase flow
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 53 ? the next sequential address se lects a byte on the same physical row as the current byte being programmed. a row of flash memory consists of 64 bytes. a byte within a row is selected by addresses a5 through a0. a new row begins wh en addresses a5 through a0 are all zero. the first byte of a series of sequential bytes being pr ogrammed in burst mode will take the same amount of time to program as a byte progr ammed in standard mode. subsequent bytes will program in the burst program time provided that the condi tions above are met. in the case the next sequential address is the beginning of a new row, the pr ogram time for that byte will be the st andard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command complete s, then the charge pump will be disabled and high voltage removed from the array. figure 4-3. flash burst program flowchart 1 0 fcbef ? start write to flash to buffer address and data write command (0x25) to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (note 2) no yes new burst command ? 1 0 fccf ? error exit done note 2: wait at least four bus cycles before 1 0 faccerr ? clear error faccerr ? note 1: required only once after reset. write to fcdiv (note 1) checking fcbef or fccf. flash burst program flow
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 54 freescale semiconductor 4.4.5 access errors an access error occurs whenever the co mmand execution protocol is violated. any of the following specif ic actions will cause the access error fl ag (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to facce rr in fstat before any command can be processed. ? writing to a flash address before the internal flash clock frequency has been set by writing to the fcdiv register ? writing to a flash address whil e fcbef is not set (a new comm and cannot be st arted until the command buffer is empty.) ? writing a second time to a flas h address before launching the pr evious command (there is only one write to flash for every command.) ? writing a second time to fcmd before launching the previous co mmand (there is only one write to fcmd for every command.) ? writing to any flash control register other than fcmd after writing to a flash address ? writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to fcmd ? writing any flash control register other than the write to fstat (to clear fcbef and launch the command) after writing the command to fcmd. ? the mcu enters stop mode while a program or er ase command is in progress (the command is aborted.) ? writing the byte program, burst program, or pa ge erase command code (0x20, 0x25, or 0x40) with a background debug command while the mcu is se cured (the background debug controller can only do blank check and mass erase co mmands when the mcu is secure.) ? writing 0 to fcbef to cancel a partial command 4.4.6 flash block protection the block protection feature preven ts the protected region of flash from program or erase changes. block protection is controlled through the flash pr otection register (fprot). when enabled, block protection begins at any 512 byt e boundary below the last addr ess of flash, 0xffff. (see section 4.6.4, ?flash protection regist er (fprot and nvprot) ?). after exit from reset, fprot is lo aded with the contents of the nvprot location, which is in the nonvolatile register block of the flash memory. fprot cannot be changed directly from application software so a runaway program ca nnot alter the block protection setti ngs. because nvprot is within the last 512 bytes of flash, if any amount of memory is protected, nvprot is it self protected and cannot be altered (intentionally or unint entionally) by the application soft ware. fprot can be written through background debug commands, which allo ws a way to erase and reprogram a protected flash memory. the block protection mechan ism is illustrated in figure 4-4 . the fps bits are used as the upper bits of the last address of unprotected memory. this address is formed by c oncatenating fps7:fps1 with logic 1 bits as shown. for example, to protec t the last 1536 bytes of memory (a ddresses 0xfa00 through 0xffff), the fps bits must be set to 1111 100, which results in the value 0xf9ff as the last address of unprotected
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 55 memory. in addition to programming the fps bits to the appropriate value, fpdis (bit 0 of nvprot) must be programmed to logic 0 to enable block pr otection. therefore the valu e 0xf8 must be programmed into nvprot to protect addresses 0xfa00 through 0xffff. figure 4-4. block protection mechanism one use for block protection is to block protect an area of flash me mory for a bootloader program. this bootloader program then can be used to erase the re st of the flash memory and reprogram it. because the bootloader is protected, it remain s intact even if mcu power is lost in the middle of an erase and reprogram operation. 4.4.7 vector redirection whenever any block protection is en abled, the reset and interrupt v ectors will be protected. vector redirection allows users to modify interrupt vector information wit hout unprotecting bootloader and reset vector space. vector redi rection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to zero. for redirection to o ccur, at least some portion but not all of the flash memory must be block protected by programming the nvprot register located at address 0xffbd. all of the interrupt vectors (memor y locations 0xffc0?0xfffd) are redi rected, though the reset vector (0xfffe:ffff) is not. for example, if 512 bytes of flas h are protected, the protected addr ess region is fr om 0xfe00 through 0xffff. the interrupt vectors (0x ffc0?0xfffd) are redirected to th e locations 0xfdc0?0xfdfd. now, if an spi interrupt is taken for in stance, the values in the locations 0xfde0:fde1 are used for the vector instead of the values in the locations 0xffe0:ffe1. this allows the user to reprogram the unprotected portion of the flash with new progr am code including new interrupt ve ctor values while leaving the protected area, which includes the default vector locations, unchanged. 4.5 security the mc9s08ac16 series includes circ uitry to prevent unauthorized acces s to the contents of flash and ram memory. when security is enga ged, flash and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are consider ed unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory lo cation with a program executing from an unsecured memory space or through the background debug interface are bloc ked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the stat e of two nonvolatile register bits (sec01:sec00) in the fopt register. during reset, the contents of the nonvolatile location nvop t are copied from flash into the working fopt register in high-page regist er space. a user engages security by programming the nvopt location which can be done at the same time the flash memory is programmed. the 1:0 state fps7 fps6 fps5 fps4 fps3 fps2 fps1 a15 a14 a13 a12 a11 a10 a9 a8 1 a7 a6 a5 a4 a3 a2 a1 a0 111 11111
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 56 freescale semiconductor disengages security and the other thr ee combinations engage security. no tice the erased state (1:1) makes the mcu secure. during development, whenever the fl ash is erased, it is good practice to immediately program the sec00 bit to 0 in nvopt so sec01: sec00 = 1:0. this would al low the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can still be used for background memory access commands, but the mcu cannot enter active background mode except by holding bkgd/ms low at the rising edge of reset. a user can choose to allow or disallow a securi ty unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile ke yen bit in nvopt/fopt is 0, the b ackdoor key is disabled and there is no way to disengage security without completely erasing all flash locations. if keyen is 1, a secure user program can temporar ily disengage security by: 1. writing 1 to keyacc in the fcnfg register. th is makes the flash module interpret writes to the backdoor comparison key locations (nvbac kkey through nvbackkey+7) as values to be compared against the key rather than as the first step in a flash pr ogram or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be done in order starting with the value for nvbackkey and ending with nvbackkey+7. sthx should not be used for thes e writes because these writes cannot be done on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication in terface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was just written matches the key stored in the flash locations, sec01:sec00 are automatically change d to 1:0 and security will be disengaged until the next reset. the security key can be wr itten only from secure memory (either ra m or flash), so it cannot be entered through background commands without the cooperation of a secure user program. the backdoor comparison key (nvbackkey through nvbackkey+7) is locate d in flash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other flash memory lo cation. the nonvolatile registers ar e in the same 512-byte block of flash as the reset and inte rrupt vectors, so block protecting that space also block protects the backdoor comparison key. block protec ts cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechan ism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through th e background debug interfac e by taking these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec01:sec00 = 1:0.
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 57 4.6 flash registers and control bits the flash module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in flash me mory which are copied into th ree corresponding high-page control registers at reset. there is also an 8-byt e comparison key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignme nts for all flash registers. this section refers to registers and control bits only by their names. a fr eescale-provided equate or header fi le normally is used to translate these names into the appropriate absolute addresses. 4.6.1 flash clock divider register (fcdiv) bit 7 of this register is a read-onl y status flag. bits 6 through 0 may be read at any time but can be written only one time. before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. if prdiv8 = 0 ? f fclk = f bus ([div5:div0] + 1) eqn. 4-1 if prdiv8 = 1 ? f fclk = f bus (8 ([div5:div0] + 1)) eqn. 4-2 table 4-7 shows the appropriate values for prdiv8 and div5:div0 for sele cted bus frequencies. 76543210 rdivld prdiv8 div5 div4 div3 div2 div1 div0 w reset00000000 = unimplemented or reserved figure 4-5. flash clock divider register (fcdiv) table 4-6. fcdiv regist er field descriptions field description 7 divld divisor loaded status flag ? when set, this read-only status flag indicates that the fcdiv register has been written since reset. reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been written since reset; erase and program operations disabled for flash. 1 fcdiv has been written since reset; erase and program operations enabled for flash. 6 prdiv8 prescale (divide) flash clock by 8 0 clock input to the flash clock divider is the bus rate clock. 1 clock input to the flash clock divider is the bus rate clock divided by 8. 5:0 div[5:0] divisor for flash clock divider ? the flash clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div5:div0 field plus one. the resulting frequency of the internal flash clock must fall within the range of 200 khz to 150 khz for proper flash operations. program/erase timing pulses are one cycle of this inter nal flash clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer nu mber of these pulses to complete an erase or program operation. see equation 4-1 , equation 4-2 , and ta bl e 4 - 6 .
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 58 freescale semiconductor 4.6.2 flash options register (fopt and nvopt) during reset, the contents of the nonvolatile locati on nvopt are copied from flash into fopt. bits 5 through 2 are not used and always read 0. this register may be read at a ny time, but writes have no meaning or effect. to change the value in this register, er ase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. table 4-7. flash clock divider settings f bus prdiv8 (binary) div5:div0 (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s 76543210 r keyen fnored 0 0 0 0 sec01 sec00 w reset this register is loaded from nonvolatile location nvopt during reset. = unimplemented or reserved figure 4-6. flash options register (fopt) table 4-8. fopt register field descriptions field description 7 keyen backdoor key mechanism enable ? when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) firmware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to section 4.5, ?security .? 0 no backdoor key access allowed. 1 if user firmware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is te mporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ? when this bit is 1, then vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled. 1:0 sec0[1:0] security state code ? this 2-bit field determines the security state of the mcu as shown in ta bl e 4 - 9 . when the mcu is secure, the contents of ram and flash memo ry cannot be accessed by instructions from any unsecured source including the background debug interface. for more detailed information about security, refer to section 4.5, ?security .?
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 59 sec01:sec00 changes to 1:0 after su ccessful backdoor key entry or a successful blank check of flash. 4.6.3 flash configuration register (fcnfg) bits 7 through 5 may be read or wri tten at any time. bits 4 through 0 al ways read 0 and cannot be written. table 4-9. security states sec01:sec00 description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 76543210 r0 0 keyacc 00000 w reset00000000 = unimplemented or reserved figure 4-7. flash configuration register (fcnfg) table 4-10. fcnfg register field descriptions field description 5 keyacc enable writing of access key ? this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to section 4.5, ?security .? 0 writes to 0xffb0?0xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?0xffb7) are interpreted as comparison key writes.
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 60 freescale semiconductor 4.6.4 flash protection register (fprot and nvprot) during reset, the contents of th e nonvolatile location nvprot are copi ed from flash into fprot. this register can be read at any time. if fpdis = 0, protect ion can be increased, i.e., a smaller value of fps can be written. if fpdis = 1, writ es do not change protection. 4.6.5 flash status register (fstat) bits 3, 1, and 0 always read 0 and writes have no meani ng or effect. the remaining fi ve bits are status bits that can be read at any time. writes to these bits have special meanings that are discussed in the bit descriptions. 76543210 r fps 1 fpdis 1 w reset this register is loaded from nonvolatile location nvprot during reset. 1 background commands can be used to change the contents of these bits in fprot. figure 4-8. flash protection register (fprot) table 4-11. fprot register field descriptions field description 7:1 fps[7:1] flash protect select bits ? when fpdis = 0, this 7-bit field determ ines the ending address of unprotected flash locations at the high address end of the flash. protected flash locations cannot be erased or programmed. 0 fpdis flash protection disable 0 flash block specified by fps[ 7:1] is block protected (program and erase not allowed). 1 no flash block is protected. 76543210 r fcbef fccf fpviol faccerr 0fblank0 0 w reset11000000 = unimplemented or reserved figure 4-9. flash status register (fstat)
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 61 4.6.6 flash command register (fcmd) only five command codes are recognized in normal us er modes as shown in table 4-14 . refer to section 4.4.3, ?program and erase command execution ? for a detailed discussion of flash programming and erase operations. table 4-12. fstat regist er field descriptions field description 7 fcbef flash command bu ffer empty flag ? the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a one to it or when a burst program command is transferred to the array for programming. only bu rst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command may be written to the command buffer. 6 fccf flash command complete flag ? fccf is set automatically when t he command buffer is empty and no command is being processed. fccf is cleared automatically when a new co mmand is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 0 command in progress 1 all commands complete 5 fpviol protection violation flag ? fpviol is set automatically when fcbef is cleared to register a command that attempts to erase or program a location in a protecte d block (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location. 4 faccerr access error flag ? faccerr is set automatically when the pr oper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or eras e operation is attempted befo re the fcdiv register has been initialized, or if the mcu enters stop while a comm and was in progress. for a more detailed discussion of the exact actions that are considered access errors, see section 4.4.5, ?access errors .? faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 0 no access error. 1 an access error has occurred. 2 fblank flash verified as al l blank (erased) flag ? fblank is set automatically at the conclusion of a blank check command if the entire flash array was verified to be eras ed. fblank is cleared by clearing fcbef to write a new valid command. writing to fblank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash array is completely erased (all 0xff). 76543210 r 00000000 w fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 reset00000000 figure 4-10. flash command register (fcmd)
chapter 4 memory mc9s08ac16 series data sheet, rev. 8 62 freescale semiconductor all other command codes are illega l and generate an access error. it is not necessary to perform a blank check comma nd after a mass erase operation. only blank check is required as part of the se curity unlocking mechanism. table 4-13. fcmd register field descriptions field description 7:0 fcmd[7:0] flash command bits ? see ta b l e 4 - 1 4 table 4-14. flash commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog byte program ? burst mode 0x25 mburstprog page erase (512 bytes/page) 0x40 mpageerase mass erase (all flash) 0x41 mmasserase
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 63 chapter 5 resets, interrupts, and system configuration 5.1 introduction this chapter discusses basic reset a nd interrupt mechanisms and the vari ous sources of reset and interrupts in the mc9s08ac16 series. some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data manual. this chapter gathers basic information a bout all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog and real-time interrupt (rti), are not part of on-chip peripheral systems with their own se ctions but are part of the system control logic. 5.2 features reset and interrupt features include: ? multiple sources of reset for flexible sy stem configuration an d reliable operation: ? power-on detection (por) ? low voltage detection (lvd) with enable ? external reset pin ? cop watchdog with enable and two timeout choices ? illegal opcode ? illegal address ? serial command from a background debug host ? reset status register (srs) to indicate source of most recent reset ? separate interrupt vectors for each module (reduces polling overhead) (see table 5-11 ) 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers ar e forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral m odules are disabled and i/o pins are initially configured as general-purpose high-impedance input s with pullup devices disa bled. the i bit in the condition code register (ccr) is se t to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system c ontrol settings. sp is forced to 0x00ff at reset. the following sources of reset are available on the mc9s08ac16 series: ? power-on reset (por) ? low-voltage detect (lvd)
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 64 freescale semiconductor ? computer operating properly (cop) timer ? illegal opcode detect ? illegal address detect ? background debug forced reset ? the reset pin (reset ) ? clock generator loss of lock and loss of clock reset each of these sources, with the ex ception of the background debug forced reset, has an associated bit in the system reset status register. 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset wh en the application software fails to execute as expected. to prevent a system reset from the cop time r (when it is enabled), ap plication software must reset the cop counter periodically. if the application pr ogram gets lost and fails to reset the cop counter before it times out, a sy stem reset is generated to force the system back to a known starting point. after any reset, the cope becomes set in sopt enabling th e cop watchdog (see section 5.9.4, ?system options register (sopt) ,? for additional information). if the co p watchdog is not used in an application, it can be disabled by clear ing cope. the cop counter is reset by wr iting any value to th e address of srs. this write does not affect the data in the read-only srs. instead, the act of writing to this address is decoded and sends a reset signal to the cop counter. the copclks bit in sopt2 (see section 5.9.10, ?system options register 2 (sopt2) ,? for additional information) selects the clock sour ce used for the cop timer. the cloc k source options are either the bus clock or an internal 1-khz clock s ource. with each clock source, ther e is an associated short and long time-out controlled by copt in sopt. table 5-1 summaries the control func tions of the copclks and copt bits. the cop watchdog defaults to operation from the bus clock source and the associated long time-out (2 18 cycles). even if the application will use th e reset default settings of cope, copclks, and copt, the user must write to the write-once sopt and sopt 2 registers during reset initializati on to lock in the settings. that way, they cannot be changed accidenta lly if the application program gets lost. the initial writes to sopt and sopt2 will rese t the cop counter. table 5-1. cop configuration options control bits clock source cop overflow count copclks copt 00 ~1 khz 2 5 cycles (32 ms) 1 1 values are shown in this column based on t rti =1ms. see t rti in the appendix section a.10.1, ?control timing ,? for the tolerance of this value. 01 ~1 khz 2 8 cycles (256 ms) 1 10 bus 2 13 cycles 11 bus 2 18 cycles
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 65 the write to srs that services (cle ars) the cop counter must not be pl aced in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. in background debug mode, the cop counter will not increment. when the bus clock source is selected, the cop coun ter does not increment while the system is in stop mode. the cop counter resumes as soon as the mcu exits stop mode. when the 1-khz clock source is sel ected, the cop counter is re-initialized to zer o upon entry to stop mode. the cop counter begins from zer o after the mcu exits stop mode. 5.5 interrupts interrupts provide a way to save the current cpu status and registers, ex ecute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instru ction, interrupts are caus ed by hardware events such as an edge on the irq pin or a timer-overflow event. the debug module can also generate an swi under certain ci rcumstances. if an event occurs in an enabled interrupt source, an associated read-onl y status flag will become set. the cpu will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. the i bit in the ccr is 0 to allow interrupts. the global inte rrupt mask (i bit) in the ccr is initially set after reset which masks (prevents) all maskable interrupt s ources. the user program in itializes the stack pointer and performs other system setup be fore clearing the i bit to allo w the cpu to respond to interrupts. when the cpu receives a qua lified interrupt request, it completes the current in struction before responding to the interrupt. the interrupt sequence obeys the sa me cycle-by-cycle sequence as the swi instruction and consists of: ? saving the cpu registers on the stack ? setting the i bit in the ccr to mask further interrupts ? fetching the interrupt vector for the highest-p riority interrupt that is currently pending ? filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restor ed from the value stacked on entry to the isr. in rare cases, the i bit may be cleared inside an isr (after clearing the stat us flag that generated the interrupt) so that other interrupts can be serviced without waiting for the fi rst service routine to finish. this practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. the interrupt service routine ends wi th a return-from-interrupt (rti) in struction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information off the stack.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 66 freescale semiconductor note for compatibility with the m68hc08, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the interrupt service r outine (isr) and rest ore it immediately before the rti that is used to return from the isr. when two or more interrupts are pending when the i bit is cleared, the highest prio rity source is serviced first (see table 5-2 ). 5.5.1 interrupt stack frame figure 5-1 shows the contents and organizat ion of a stack frame. before the interrupt, the stack pointer (sp) points at the next av ailable byte location on the stack. the curr ent values of cpu registers are stored on the stack starting with the low-order byte of the pr ogram counter (pcl) and ending with the ccr. after stacking, the sp points at the next avai lable location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed ne xt if the interrupt had not occurred. figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu fills the instruction pipeline by reading th ree bytes of program information, starting from the pc address recovered from the stack. the status flag causing the interrupt must be acknow ledged (cleared) before returning from the isr. typically, the flag should be cleared at the beginning of the isr so that if another interrupt is generated by this same source, it will be registered so it can be serviced after comp letion of the current isr. 5.5.2 external interrupt request (irq) pin external interrupts are managed by the irq status and control register, irqsc. when the irq function is enabled, synchronous logic m onitors the pin for edge- only or edge-and-level events. when the mcu is in condition code register accumulator index register (low byte x) program counter high * high byte (h) of index regist er is not automatically stacked. * program counter low 2 2 2 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 67 stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. 5.5.2.1 irq pin configuration options the irq pin enable (irqpe) control bi t in irqsc must be 1 in order for the irq pin to act as the interrupt request (irq) input. as an irq input, the user can choose the polarity of edge s or levels detected (irqedg), whether the pin detects edges-only or e dges and levels (irqmod), and whether an event causes an interrupt or onl y sets the irqf flag which can be polled by software. the irq pin, when enabled, defaults to use an internal pull device (irqpdd = 0) , the device is a pull-up or pull-down depending on the polarity chosen. if the user desires to use an ex ternal pull-up or pull-down, the irqpdd can be written to a 1 to turn off the internal device. bih and bil instructions may be used to detect the level on the irq pin when the pin is configured to act as the irq input. note this pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the in ternally pulled up irq pin may be as low as v dd ? 0.7 v. the internal gates c onnected to this pin are pulled all the way to v dd . note when enabling the irq pin for use, th e irqf will be set, and should be cleared prior to enabling the interrupt. when configuring the pin for falling edge and level sensitivity in a 5v system, it is necessary to wait at least 6 cycles between clearing the fl ag and enabling the interrupt. 5.5.2.2 edge and level sensitivity the irqmod control bit reconfigures the detection logic so it detects edge events and pin levels. in the edge and level detection m ode, the irqf status flag becomes set wh en an edge is detected (when the irq pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the irq pin remains at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-2 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byt e of the address for the interrupt service routine is located at the first address in the vector address column, and the lo w-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated flag bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will finish the current instruction, stack th e pcl, pch, x, a, and ccr cpu registers, set the i bit, and then fetch the interru pt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 68 freescale semiconductor table 5-2. vector summary vector priority vector no. address (high/low) vector name module source enable description lower higher 29 ? 31 0xffc0/ffc1 ? 0xffc4/0xffc5 unused vector space (available for user program) 28 0xffc6/ffc7 vtpm3ovf tpm3 tof toie tpm3 overflow 27 0xffc8/ffc9 vtpm3ch1 tpm3 ch1f ch1ie tpm3 channel 1 26 0xffca/ffcb vtpm3ch0 tpm3 ch0f ch0if tpm3 channel 0 25 0xffcc/ffcd vrti system control rtif rtie real-time interrupt 24 0xffce/ffcf viic1 iic1 iicif iicie iic1 23 0xffd0/ffd1 vadc1 adc1 coco aien adc1 22 0xffd2/ffd3 vkeyboard 1 kbi kbf kbie kbi pins 21 0xffd4/ffd5 vsci2tx sci2 tdre tc tie tcie sci2 transmit 20 0xffd6/ffd7 vsci2rx sci2 idle rdrf ilie rie sci2 receive 19 0xffd8/ffd9 vsci2err sci2 or nf fe pf orie nfie feie pfie sci2 error 18 0xffda/ffdb v sci1tx sci1 tdre tc tie tcie sci1 transmit 17 0xffdc/ffdd vsci1rx sci1 idle rdrf ilie rie sci1 receive 16 0xffde/ffdf vsci1err sci1 or nf fe pf orie nfie feie pfie sci1 error 15 0xffe0/ffe1 vspi1 spi1 spif modf sptef spie spie sptie spi1 14 0xffe2/ffe3 vtpm2ovf tpm2 tof toie tpm2 overflow 13 0xffe4/ffe5 vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 12 0xffe6/ffe7 vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 11 0xffe8/ffe9 vtpm1ovf tpm1 tof toie tpm1 overflow 10 0xffea/ffeb unused vector space 9 0xffec/ffed unused vector space 8 0xffee/ffef vtpm1ch3 tpm1 ch3f ch3ie tpm1 channel 3 7 0xfff0/fff1 vtpm1ch2 tpm1 ch2f ch2ie tpm1 channel 2 6 0xfff2/fff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 5 0xfff4/fff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 4 0xfff6/fff7 vicg icg icgif (lols/locs) lolre/locre icg 3 0xfff8/fff9 vlvd system control lvdf lvdie low-voltage detect 2 0xfffa/fffb virq irq irqf irqie irq pin 1 0xfffc/fffd vswi core swi instruction ? software interrupt 0 0xfffe/ffff vreset system control cop lv d reset pin illegal opcode cope lvdre ? ? watchdog timer low-voltage detect external pin illegal opcode
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 69 5.6 low-voltage detect (lvd) system the mc9s08ac16 series includes a system to protect against low voltage conditi ons in order to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) ci rcuit and an lvd circuit with a user selectable trip voltage, either high (v lvdh ) or low (v lvdl ). the lvd circuit is enabled when lv de in spmsc1 is high and the trip voltage is selected by lvdv in spmsc2. the lvd is disabled upon entering any of the stop modes unless the lvdse bit is set. if lvdse and lvde are both set, then the mcu cannot enter stop2, and the current consumption in stop3 with the lvd enabled will be greater. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the v por level, the por circuit will cause a rese t condition. as the supply voltage rises, the lvd circuit will hold the chip in reset until the supply has risen above the v lvdl level. both the por bit and the lvd bit in srs are set following a por. 5.6.2 lvd reset operation the lvd can be configured to generate a reset upon detection of a low vol tage condition by setting lvdre to 1. after an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the level determined by lvdv . the lvd bit in the srs register is set following either an lvd reset or por. 5.6.3 lvd interrupt operation when a low voltage condition is dete cted and the lvd circuit is configured for interrupt operation (lvde set, lvdie set, and lvdre clear), then lvdf will be set and an lvd interrupt will occur. 5.6.4 low-voltage warning (lvw) the lvd system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is still above, the lvd voltage. the lv w does not have an interr upt associated with it. there are two user sel ectable trip voltages for the lvw, one high (v lvwh ) and one low (v lvwl ). the trip voltage is selected by lvwv in spmsc2. setting the lv w trip voltage equal to the lvd trip voltage is not recommended. typical use of the lvw would be to select v lvwh and v lvdl . 5.7 real-time interrupt (rti) the real-time interrupt function ca n be used to generate periodic interrupts. the rti can accept two sources of clocks, the 1-khz internal clock or an external clock if av ailable. the 1-khz internal clock source is completely independent of any bus clock source and is used only by the rti m odule and, on some mcus, the cop watchdog. to use an exte rnal clock source, it must be available and active. the rticlks bit in srtisc is used to select the rti clock source.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 70 freescale semiconductor either rti clock source can be used when the mcu is in run, wait or stop3 mode. when using the external oscillator in stop3, it must be en abled in stop (oscsten = 1) and configured fo r low bandwidth operation (range = 0). only the internal 1-khz clock source ca n be selected to wake the mcu from stop2 mode. the srtisc register includes a r ead-only status flag, a write-only ac knowledge bit, and a 3-bit control value (rtis2:rtis1:rtis0) used to disable the clock source to the real-time inte rrupt or select one of seven wakeup periods. the rti has a local interrupt enable, rtie, to allow ma sking of the real-time interrupt. the rti can be disabled by writing each bit of rtis to zeroes, and no interrupts will be generated. see section 5.9.7, ?system real-time interrupt status and control register (srtisc) ,? for detailed information about this register. 5.8 mclk output the ptc2 pin is shared with the mclk clock output . setting the pin enable bit, mpe, causes the ptc2 pin to output a divided version of the internal mc u bus clock. the divide ratio is determined by the mcsel bits. when mpe is set, the ptc2 pin is forced to operate as an output pi n regardless of the state of the port data direction control bit for the pin. if the mcsel bits are all 0s, th e pin is driven low. the slew rate and drive strength for the pin are cont rolled by ptcse2 and ptcds2, respectively. the maximum clock output frequency is limi ted if slew rate control is enabled, see the electrical chapter for pin rise and fall times with slew rate enabled. 5.9 reset, interrupt, and system co ntrol registers and control bits one 8-bit register in the direct page register space a nd eight 8-bit registers in th e high-page register space are related to reset and interrupt systems. refer to the direct-page register summary in chapter 4, ?memory ,? of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. some control bits in the sopt and spmsc2 registers are related to m odes of operation. although brief descriptions of these bits are pr ovided here, the related functions are discussed in greater detail in chapter 3, ?modes of operation .?
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 71 5.9.1 interrupt pin request status and control register (irqsc) this direct page register includes status and control bits which are used to configure the irq function, report status, and acknowledge irq events. 76543210 r0 irqpdd irqedg irqpe irqf 0 irqie irqmod w irqack reset00000000 = unimplemented or reserved figure 5-2. interrupt request status and control register (irqsc) table 5-3. irqsc regist er field descriptions field description 6 irqpdd interrupt request (irq) pull device disable ? this read/write control bit is used to disable the internal pull-up/pull-down device when the irq pin is enabled (irqpe = 1) allowing for an external device to be used. 0 irq pull device enabled if irqpe = 1. 1 irq pull device disabled if irqpe = 1. 5 irqedg interrupt request (irq) edge select ? this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or only edges. when the ir q pin is enabled as the irq input and is configured to detect rising edges, it has a pull-down. when the irq pin is enabled as the irq input and is configured to detect falling edges, it has a pull-up. 0 irq is falling edge or falling edge/low-level sensitive. 1 irq is rising edge or rising edge/high-level sensitive. 4 irqpe irq pin enable ? this read/write control bit enables the irq pin function. when this bit is set the irq pin can be used as an interrupt request. 0 irq pin function is disabled. 1 irq pin function is enabled. 3 irqf irq flag ? this read-only status bit indicates when an interrupt request event has occurred. 0 no irq request. 1 irq event detected. 2 irqack irq acknowledge ? this write-only bit is used to acknowledge in terrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return 0. if edge-and-level detecti on is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. 1 irqie irq interrupt enable ? this read/write control bit determines whether irq events generate an interrupt request. 0 interrupt request when irqf set is disabled (use polling). 1 interrupt requested whenever irqf = 1. 0 irqmod irq detection mode ? this read/write control bit selects eith er edge-only detection or edge-and-level detection. the irqedg control bit determines the polarity of edges and levels that are detected as interrupt request events. see section 5.5.2.2, ?edge and level sensitivity ? for more details. 0 irq event on falling edges or rising edges only. 1 irq event on falling edges and low levels or on rising edges and high levels.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 72 freescale semiconductor 5.9.2 system reset status register (srs) this register includes seven read-only status flags to indicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdf r register, none of the status bits in srs will be set. writing any value to this register address clears the cop watchdog timer without affecting the contents of this register. the reset state of thes e bits depends on what caused the mcu to reset. 76543210 r por pin cop ilop ilad icg lvd 0 w writing any value to srs address clears cop watchdog timer. por10000010 lvr: u0000010 any other reset: 0note 1 note 1 note 1 0note 1 00 u = unaffected by reset 1 any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that are not acti ve at the time of reset will be cleared. figure 5-3. system reset status (srs) table 5-4. srs register field descriptions field description 7 por power-on reset ? reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvr) status bit is also set to indicate that the reset occurred while the internal supply was below the lvr threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ? reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. 5 cop computer operating properly (cop) watchdog ? reset was caused by the cop watchdog timer timing out. this reset source may be blocked by cope = 0. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode ? reset was caused by an attempt to execut e an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt regi ster. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 73 5.9.3 system background debug force reset register (sbdfr) this register contains a single write-only c ontrol bit. a serial background command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. 3 ilad illegal address ? reset was caused by an attempt to access a designated illegal address. 0 reset not caused by an illegal address access. 1 reset caused by an illegal address access. illegal address areas in the mc9s08ac16 are: 0x0470 - 0x17ff ? gap from end of ram to start of high page registers 0x1860 - 0xbfff ? gap from end of high page registers to start of flash memory unused and reserved locations in register areas are not considered illegal addresses and do not trigger illegal address resets. 2 icg internal clock gene ration module reset ? reset was caused by an icg module reset. 0 reset not caused by icg module. 1 reset caused by icg module. 1 lv d low voltage detect ? if the lvdre and lvdse bits are set and the supply drops below the lvd trip voltage, an lvd reset will occur. this bit is also set by por. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por. 76543210 r00000000 w bdfr 1 reset00000000 = unimplemented or reserved 1 bdfr is writable only through serial backgro und debug commands, not from user programs. figure 5-4. system background debug force reset register (sbdfr) table 5-5. sbdfr register field descriptions field description 0 bdfr background debug force reset ? a serial background command such as write_byte may be used to allow an external debug host to force a target system reset. writing logic 1 to this bit forces an mcu reset. this bit cannot be written from a user program. table 5-4. srs register field descriptions (continued) field description
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 74 freescale semiconductor 5.9.4 system options register (sopt) this register may be read at any time. bits 3 a nd 2 are unimplemented and always read 0. this is a write-once register so only the first write after reset is honored. any subs equent attempt to write to sopt (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt should be written during the us er?s reset initialization program to set th e desired controls even if the desired settings are the same as the reset settings. 76543210 r cope copt stope 00 w reset11010011 = unimplemented or reserved figure 5-5. system options register (sopt) table 5-6. sopt regist er field descriptions field description 7 cope cop watchdog enable ? this write-once bit defaults to 1 after reset. 0 cop watchdog timer disabled. 1 cop watchdog timer enabled (force reset on timeout). 6 copt cop watchdog timeout ? this write-once bit defaults to 1 after reset. 0 short timeout period selected. 1 long timeout period selected. 5 stope stop mode enable ? this write-once bit defaults to 0 after rese t, which disables stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled.1stop mode enabled.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 75 5.9.5 system mclk control register (smclk) this register is used to control the mclk clock output. 5.9.6 system device identificati on register (sdidh, sdidl) this read-only register is included so host developm ent systems can identify the hcs08 derivative and revision number. this allows the development soft ware to recognize where specific memory blocks, registers, and control bits are located in a target mcu. figure 5-7. system device identification register ? high (sdidh) 76543210 r000 mpe 0 mcsel w reset00000000 = unimplemented or reserved figure 5-6. system mclk control register (smclk) table 5-7. smclk regist er field descriptions field description 4 mpe mclk pin enable ? this bit is used to enable the mclk function. 0 mclk output disabled. 1 mclk output enabled on ptc2 pin. 2:0 mcsel mclk divide select ? these bits are used to select the divide ratio for the mclk output according to the formula below when the mcsel bits are not equal to all zeroes. in the case that the mcsel bits are all zero and mpe is set, the pin is driven low. see equation 5-1 . mclk frequency = bus clock frequency (2 * mcsel) eqn. 5-1 76543210 r id11 id10 id9 id8 w reset ???? 0000 = unimplemented or reserved table 5-8. sdidh register field descriptions field description 7:4 reserved bits 7:4 are reserved. reading these bi ts will result in an indetermina te value; writes have no effect. 3:0 id[11:8] part identification number ? each derivative in the hcs08 family has a unique identification number. the mc9s08ac16 series is hard coded to t he value 0x012. see also id bits in ta bl e 5 - 9 .
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 76 freescale semiconductor 5.9.7 system real-time interrupt stat us and control register (srtisc) this register contains one read- only status flag, one wr ite-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w reset00010010 = unimplemented or reserved figure 5-8. system device identification register ? low (sdidl) table 5-9. sdidl register field descriptions field description 7:0 id[7:0] part identification number ? each derivative in the hcs08 family has a unique identification number. the mc9s08ac16 series is hard coded to t he value 0x012. see also id bits in ta bl e 5 - 8 . 76543210 rrtif 0 rticlks rtie 0 rtis2 rtis1 rtis0 w rtiack reset00000000 = unimplemented or reserved figure 5-9. system rti status and control register (srtisc) table 5-10. srtisc register field descriptions field description 7 rtif real-time interrupt flag ? this read-only status bit indicates the periodic wakeup timer has timed out. 0 periodic wakeup timer not timed out. 1 periodic wakeup timer timed out. 6 rtiack real-time interrupt acknowledge ? this write-only bit is used to ac knowledge real-time interrupt request (write 1 to clear rtif). writing 0 has no meaning or effect. reads always return logic 0. 5 rticlks real-time interrupt clock select ? this read/write bit selects the cloc k source for the real-time interrupt. 0 real-time interrupt request clock source is internal 1-khz oscillator. 1 real-time interrupt request clock source is external clock. 4 rtie real-time interrupt enable ? this read-write bit enables real-time interrupts. 0 real-time interrupts disabled. 1 real-time interrupts enabled. 2:0 rtis[2:0] real-time interrupt delay selects ? these read/write bits select the wakeup delay for the rti. the clock source for the real-time interrupt is a self-clocked source which oscillates at about 1 khz, is independent of other mcu clock sources. using external clock source the delays will be crystal frequency divided by value in rtis2:rtis1:rtis0. see ta b l e 5 - 1 1 .
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 77 5.9.8 system power management status and control 1 register (spmsc1) table 5-11. real-time interrupt frequency rtis2:rtis1:rtis0 1-khz clock source delay 1 1 normal values are shown in this column based on f rti = 1 khz. see appendix a, ?electrical characteristics and timing specifications ,? f rti for the tolerance on these values. using external clock source delay (crystal frequency) 0:0:0 disable periodic wakeup timer disable periodic wakeup timer 0:0:1 8 ms divide by 256 0:1:0 32 ms divide by 1024 0:1:1 64 ms divide by 2048 1:0:0 128 ms divide by 4096 1:0:1 256 ms divide by 8192 1:1:0 512 ms divide by 16384 1:1:1 1.024 s divide by 32768 7654321 1 0 rlvdf 0 lvdie lvdre 2 lv d s e 2 lv d e 2 bgbe w lv dac k reset00011100 = unimplemented or reserved 1 bit 1 is a reserved bit that must always be written to 0. 2 this bit can be written only one time af ter reset. additional writes are ignored. figure 5-10. system power management status and control 1 register (spmsc1) table 5-12. spmsc1 regist er field descriptions field description 7 lv d f low-voltage detect flag ? provided lvde = 1, this read-only status bit indicates a low-voltage detect event. 6 lv dac k low-voltage detect acknowledge ? this write-only bit is used to acknowledge low voltage detection errors (write 1 to clear lvdf). reads always return 0. 5 lv d i e low-voltage detect interrupt enable ? this read/write bit enables hardware interrupt requests for lvdf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvdf = 1. 4 lvdre low-voltage detect reset enable ? this read/write bit enables lvdf events to generate a hardware reset (provided lvde = 1). 0 lvdf does not generate hardware resets. 1 force an mcu reset when lvdf = 1.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 78 freescale semiconductor 3 lv d s e low-voltage detect stop enable ? provided lvde = 1, this read/writ e bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lv d e low-voltage detect enable ? this read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled. 0 bgbe bandgap buffer enable ? the bgbe bit is used to enable an internal buffer for the bandgap voltage reference for use by the adc module on one of its internal channels. 0 bandgap buffer disabled. 1 bandgap buffer enabled. table 5-12. spmsc1 register field descriptions (continued) field description
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 79 5.9.9 system power management status and control 2 register (spmsc2) this register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the mcu. figure 5-11. system power management status and control 2 register (spmsc2) 76543210 rlvwf 0 lv dv lv w v ppdf 0 ppdc 1 1 this bit can be written only one time after reset. additional writes are ignored. w lv wac k ppdack power-on reset: 0 (2) 2 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lv w . 0000000 lvd reset: 0 (2) 0uu0000 any other reset: 0 (2) 0uu0000 = unimplemented or reserved u = unaffected by reset table 5-13. spmsc2 regist er field descriptions field description 7 lv w f low-voltage warning flag ? the lvwf bit indicates the low voltage warning status. 0 low voltage warning not present. 1 low voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge ? the lvwack bit is the low-voltage warning acknowledge. writing a 1 to lvwack clears lvwf to a 0 if a low voltage warning is not present. 5 lv dv low-voltage detect voltage select ? the lvdv bit selects the lvd trip point voltage (v lv d ). 0 low trip point selected (v lv d = v lvd l ). 1 high trip point selected (v lvd = v lv d h ). 4 lv w v low-voltage warning voltage select ? the lvwv bit selects the lvw trip point voltage (v lv w ). 0 low trip point selected (v lv w = v lv w l ). 1 high trip point selected (v lvw = v lv w h ). 3 ppdf partial power down flag ? the ppdf bit indicates that the mcu has exited the stop2 mode. 0 not stop2 mode recovery. 1 stop2 mode recovery. 2 ppdack partial power down acknowledge ? writing a 1 to ppdack clears the ppdf bit. 0 ppdc partial power down control ? the write-once ppdc bit controls whet her stop2 or stop3 mode is selected. 0 stop3 mode enabled. 1 stop2, partial power down, mode enabled.
chapter 5 resets, interrupts, and system configuration mc9s08ac16 series data sheet, rev. 8 80 freescale semiconductor 5.9.10 system options register 2 (sopt2) this high page register contains bits to configure mcu specific features on the mc9s08ac16 series devices. 76543210 r copclks 1 0000000 w reset:10000000 = unimplemented or reserved 1 this bit can be written only one time af ter reset. additional writes are ignored. figure 5-12. system options register 2 (sopt2) table 5-14. sopt2 register field descriptions field description 7 copclks cop watchdog clock select ? this write-once bit selects the clock source of the cop watchdog. 0 internal 1-khz clock is source to cop. 1 bus clock is source to cop.
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 81 chapter 6 parallel input/output 6.1 introduction this chapter explains software cont rols related to parallel input/out put (i/o). the mc 9s08ac16 has seven i/o ports which include a total of 38 general-purpose i/o pins. see chapter 2, ?pins and connections ? for more information about the logic a nd hardware aspects of these pins. many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or keyboard interrupts. when these other modules are not controlling the port pins, they revert to general-purpose i/o control. note not all general-purpose i/o pins are av ailable on all packages. to avoid extra current drain from floating input pins, the user?s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unc onnected pins to outputs so the pins do not float.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 82 freescale semiconductor figure 6-1. block diagram highlighting parallel input/output pins ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown devi ce if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pulldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 83 6.2 features parallel i/o and pin cont rol features, depending on package choice, include: ? a total of 38 general-purpose i/o pins in seven ports ? hysteresis input buffers ? software-controlled pu llups on each input pin ? software-controlled sl ew rate output buffers ? four port a pins ? four port b pins shared with adc1 and tpm3 ? six port c pins shared with sci2, iic1, and mclk ? four port d pins shared with adc1, kbi, and tpm1 and tpm2 external clock inputs ? eight port e pins shared with sci1, tpm1, and spi1 ? five port f pins shared with tpm1 and tpm2 ? seven port g pins shared with xtal, extal, and kbi 6.3 pin descriptions the mc9s08ac16 series has a total of 38 parallel i/o pins in seven ports (pta?ptg). not all pins are bonded out in all packages. c onsult the pin assignment in chapter 2, ?pins and connections ,? for available parallel i/o pins. all of these pins are available fo r general-purpose i/o when th ey are not used by other on-chip peripheral systems. after reset, the shared peripheral func tions are disabled so th at the pins are controlled by the parallel i/o. all of the parallel i/o are confi gured as inputs (ptxddn = 0). the pi n control functions for each pin are configured as follows: slew rate control enabled (p txsen = 1), low drive streng th selected (ptxdsn = 0), and internal pullups di sabled (ptxpen = 0). the following paragraphs discuss each port and the software controls that determine each pin?s use. 6.3.1 port a figure 6-2. port a pin names port a pins are general-purpose i/o pins. parallel i/o function is cont rolled by the port a data (ptad) and data direction (ptadd) registers whic h are located in page zero register space. the pin control registers, pullup enable (ptape), slew rate control (ptase), and drive strength select (ptads) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port a bit 7654321bit 0 mcu pin:pta7rrrrpta2pta1pta0
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 84 freescale semiconductor 6.3.2 port b figure 6-3. port b pin names port b pins are general-purpose i/o pi ns. parallel i/o function is contro lled by the port b data (ptbd) and data direction (ptbdd) regi sters which are located in page zero regi ster space. the pin control registers, pullup enable (ptbpe), slew rate control (ptbse), and drive strength select (p tbds) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port b general-purpose i/o are shared with the adc and tpm3 timer channels. any pin enabled as an adc input will have the general-purpose i/o function disabled. wh en any tpm3 function is enabled, the direction (input or output) is controlled by the tpm3 and not by the da ta direction register of the parallel i/o port. refer to chapter 10, ?timer/pwm (s08tpmv3) ,? for more information about using port b pins as tpm channels. refer to chapter 14, ?analog-to-digit al converter (s08adc10v1) ? for more information about using port b as analog inputs. 6.3.3 port c figure 6-4. port c pin names port c pins are general-purpose i/o pi ns. parallel i/o function is contro lled by the port c data (ptcd) and data direction (ptcdd) regi sters which are located in page zero regi ster space. the pin control registers, pullup enable (ptcpe), slew rate control (ptcse), and drive strength select (p tcds) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port c general-purpose i/o is shared with sci2, iic, and mclk. when any shared function is enabled, the direction, input or output, is c ontrolled by the shared function and not by the data direct ion register of the parallel i/o port. also, for pins which are configured as outputs by th e shared function, the output data is controlled by the shared functi on and not by the port data register. refer to chapter 11, ?serial communicat ions interface (s08sciv4) ? for more information about using port c pins as sci pins. refer to chapter 13, ?inter-integrated circuit (s08iicv2) ? for more information about using port c pins as iic pins. refer to chapter 5, ?resets, interrupts, and system configuration ? for more information about using ptc2 as the mclk pin. port b bit 7654 3 2 1bit 0 mcu pin: rrrr ptb3/ tpm3ch0/ ad1p3 ptb2/ tpm3ch1/ ad1p2 ptb1/ ad1p1 ptb0/ ad1p0 port c bit 7653321bit 0 mcu pin: 0r ptc5/ rxd2 ptc4 ptc3/ txd2 ptc2/ mclk ptc1/ sda1 ptc0/ scl1
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 85 6.3.4 port d figure 6-5. port d pin names port d pins are general-pur pose i/o pins. parallel i/o function is controlled by the port d data (ptdd) and data direction (ptddd) registers whic h are located in page zero register space. the pin control registers, pullup enable (ptdpe), slew rate control (ptdse), and drive strength select (ptdds) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port d general-purpose i/o are shared with the adc and kbi. when any of these shared functions is enabled, the direction, input or output, is controlled by the shared function and not by the data direction register of the parallel i/o port. when a pin is shared with both the adc and a digital peripheral function, the adc has higher priority. for example, in the cas e that both the adc and the kbi are configured to use ptd7 then the pin is controlled by the adc module. refer to chapter 10, ?timer/pwm (s08tpmv3) ? for more information about using port d pins as tpm external clock inputs. refer to chapter 14, ?analog-to-digit al converter (s08adc10v1) ? for more information about using port d pins as analog inputs. refer to chapter 9, ?keyboard interrupt (s08kbiv1) ? for more information about using port d pins as keyboard inputs. 6.3.5 port e figure 6-6. port e pin names port e pins are general-purpose i/o pins. parallel i/o function is cont rolled by the port e data (pted) and data direction (ptedd) regi sters which are located in page zero regi ster space. the pin control registers, pullup enable (ptepe), slew rate c ontrol (ptese), and drive strength se lect (pteds) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port e general-purpose i/o is shared with sci1, spi, and tp m1 timer channels. when any of these shared functions is enabled, the direction, in put or output, is controlled by the shared function a nd not by the data direction register of the parallel i/o port. also, for pins which are configured as outputs by the shared function, the output data is controlled by the sh ared function and not by the port data register. port d bit 7654321bit 0 mcu pin: rrrr ptd3/ ad1p11/ kbip6 ptd2/ ad1p10/ kbip5 ptd1/ ad1p9 ptd0/ ad1p8 port e bit 7654321bit 0 mcu pin: pte7/ spsck1 pte6/ mosi1 pte5/ miso1 pte4/ ss1 pte3/ tpm1ch1 pte2/ tpm1ch0 pte1/ rxd1 pte0/ txd1
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 86 freescale semiconductor refer to chapter 11, ?serial communicat ions interface (s08sciv4) ? for more information about using port e pins as sci pins. refer to chapter 12, ?serial peripheral interface (s08spiv3) ? for more information about using port e pins as spi pins. refer to chapter 10, ?timer/pwm (s08tpmv3) ? for more information about using port e pins as tpm channel pins. 6.3.6 port f figure 6-7. port f pin names port f pins are general-pur pose i/o pins. paralle l i/o function is controlled by the port f data (ptfd) and data direction (ptfdd) registers whic h are located in page zero register space. the pin control registers, pullup enable (ptfpe), slew rate control (ptfse), and drive strength select (ptfds) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port f general-purpose i/o is shared with tpm1 a nd tpm2 timer channels. when any of these shared functions is enabled, the direction, in put or output, is controlled by the shared function a nd not by the data direction register of the parallel i/o port. also, for pins which are configured as outputs by the shared function, the output data is controlled by the sh ared function and not by the port data register. refer to chapter 10, ?timer/pwm (s08tpmv3) ? for more information about using port f pins as tpm channel pins. 6.3.7 port g figure 6-8. port g pin names port g pins are general-pur pose i/o pins. parallel i/o function is controlled by the port g data (ptgd) and data direction (ptgdd) registers whic h are located in page zero register space. the pin control registers, pullup enable (ptgpe), slew rate control (ptgse), and drive strength select (ptgds) are located in the high page registers. refer to section 6.4, ?parallel i/o control ? for more information about general-purpose i/o control and section 6.5, ?pin control ? for more information about pin control. port g general-purpose i/o is shared with kbi, xtal, and extal. when a pin is enabled as a kbi input, the pin functions as an input regardle ss of the state of the associated pt g data direction register bit. when the external oscillator is enabled, ptg5 and ptg6 func tion as oscillator pins. in this case the associated parallel i/o and pin co ntrol registers have no control of the pins. port f bit 7654321bit 0 mcu pin: rptf6 ptf5/ tpm2ch1 ptf4/ tpm2ch0 rr ptf1/ tpm1ch3 ptf0/ tpm1ch2 port g bit 7654321bit 0 mcu pin: 0 ptg6/ extal ptg5/ xtal ptg4/ kbip4 ptg3/ kbip3 ptg2/ kbip2 ptg1/ kbip1 ptg0/ kbip0
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 87 refer to chapter 8, ?internal cloc k generator (s08icgv4) ? for more information a bout using po rt g pins as xtal and extal pins. refer to chapter 9, ?keyboard interrupt (s08kbiv1) ? for more information about using port g pins as keyboard inputs. 6.4 parallel i/o control reading and writing of parallel i/o is done through the port data registers. the di rection, input or output, is controlled through the port data di rection registers. the parallel i/ o port function for an individual pin is illustrated in the block diagram below. figure 6-9. parallel i/o block diagram the data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register read s. each port pin has a data directi on register bit. when ptxddn = 0, the corresponding pin is an input and reads of ptxd return the pin value. when ptxddn = 1, the corresponding pin is an output and read s of ptxd return the last value written to the port data register. when a peripheral module or system function is in contro l of a port pin, the data di rection register bit still controls what is returned for reads of the port da ta register, even though th e peripheral system has overriding control of the actual pin direction. when a shared analog function is enabled for a pin, all digital pin functions are di sabled. a read of the port data register returns a value of 0 for any bits whic h have shared analog functi ons enabled. in general, whenever a pin is shared with both an alternate di gital function and an analog function, the analog function q d q d 1 0 port read ptxddn ptxdn output enable output data input data synchronizer data busclk
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 88 freescale semiconductor has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. it is a good programming practice to wr ite to the port data register befo re changing the direction of a port pin to become an output. this ensures that the pin wi ll not be driven momentarily with an old data value that happened to be in the port data register. 6.5 pin control the pin control registers are located in the high page register block of the memory. these registers are used to control pullups, slew rate, a nd drive strength for the i/o pins. the pin control registers operate independently of the pa rallel i/o registers. 6.5.1 internal pullup enable an internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (ptxpen). the pullup device is di sabled if the pin is configured as an output by the parallel i/o control logic or any shared peripheral functi on regardless of the state of the corresponding pullup enable register bit. the pull up device is also disabled if the pin is controll ed by an analog function. 6.5.2 output slew rate control enable slew rate control can be enabled for each port pin by setting the corres ponding bit in one of the slew rate control registers (ptxsen). when enab led, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pins which are configured as inputs. 6.5.3 output drive strength select an output pin can be selected to have high output drive strength by set ting the corresponding bit in one of the drive strength select registers (p txdsn). when high drive is selected a pin is capable of sourcing and sinking greater current. even though ev ery i/o pin can be selected as high drive, the user must ensure that the total current source a nd sink limits for the chip are not exceed ed. drive strength se lection is intended to affect the dc behavior of i/o pi ns. however, the ac behavior is al so affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this the emc emi ssions may be affected by en abling pins as high drive.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 89 6.6 pin behavior in stop modes depending on the stop mode, i/o functi ons differently as the result of executing a stop instruction. an explanation of i/o behavior fo r the various stop modes follows: ? stop2 mode is a partial power-down mode, whereby i/o latches are maintained in their state as before the stop instruction was ex ecuted. cpu register status and the state of i/o registers should be saved in ram before the st op instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user shoul d examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initia lized as if a pow er on reset had occurred. if the ppdf bit is 1, i/o data previously stored in ram, before the stop instruction was executed, peripherals may require being initiali zed and restored to their pre-stop condition. the user must then write a 1 to the ppdack bit in th e spmsc2 register. access to i/o is now permitted again in the user?s application program. ? in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user. 6.7 parallel i/o and pin control registers this section provides information about the registers associated with the parallel i/o ports and pin control functions. these parallel i/o regist ers are located in page zero of th e memory map and the pin control registers are located in the high pa ge register section of memory. refer to tables in chapter 4, ?memory ,? for the absolute address assign ments for all parallel i/o and pin control registers. this section refe rs to registers and control bits onl y by their names. a freescale-provided equate or header file nor mally is used to translate these names into the appropriate absolute addresses. 6.7.1 port a i/o registers (ptad and ptadd) port a parallel i/o function is cont rolled by the registers listed below. 76543210 r ptad7 r r r r ptad2 ptad1 ptad0 w reset00000000 figure 6-10. port a data register (ptad) 1 1 bits 6 through 3 are reserved bits that must always be written to 0. table 6-1. ptad register field descriptions field description 7, 2:0 ptadn port a data register bits ? for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port a pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins be cause reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 90 freescale semiconductor 6.7.2 port a pin control registers (ptape, ptase, ptads) in addition to the i/o control, port a pins are controlled by the registers listed below. 76543210 r ptadd7 r r r r ptadd2 ptadd1 ptadd0 w reset00000000 figure 6-11. data direction for port a register (ptadd) 1 1 bits 6 through 3 are reserved bits that must always be written to 0. table 6-2. ptadd register field descriptions field description 7, 2:0 ptaddn data direction for port a bits ? these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn. 76543210 r ptape7 r r r r ptape2 ptape1 ptape0 w reset00000000 figure 6-12. internal pullup enable for port a (ptape) 1 1 bits 6 through 3 are reserved bits that must always be written to 0. table 6-3. ptape register field descriptions field description 7, 2:0 ptapen internal pullup enable for port a bits ? each of these control bits determines if the internal pullup device is enabled for the associated pta pin. for port a pins that are configured as outputs, t hese bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port a bit n. 1 internal pullup device enabled for port a bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 91 76543210 r ptase7 r r r r ptase2 ptase1 ptase0 w reset00000000 figure 6-13. output slew rate control enable for port a (ptase) 1 1 bits 6 through 3 are reserved bits that must always be written to 0. table 6-4. ptase register field descriptions field description 7, 2:0 ptasen output slew rate control enable for port a bits ? each of these control bits determine whether output slew rate control is enabled for the associated pta pin. for po rt a pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port a bit n. 1 output slew rate control enabled for port a bit n. 76543210 r ptads7 r r r r ptads2 ptads1 ptads0 w reset00000000 figure 6-14. output drive strength selection for port a (ptads) 1 1 bits 6 through 3 are reserved bits that must always be written to 0. table 6-5. ptads regist er field descriptions field description 7, 2:0 ptadsn output drive strength selection for port a bits ? each of these control bits selects between low and high output drive for the associated pta pin. 0 low output drive enabled for port a bit n. 1 high output drive enabled for port a bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 92 freescale semiconductor 6.7.3 port b i/o registers (ptbd and ptbdd) port b parallel i/o function is contro lled by the registers in this section. 76543210 r r r r r ptbd3 ptbd2 ptbd1 ptbd0 w reset00000000 figure 6-15. port b data register (ptbd) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-6. ptbd regist er field descriptions field description 3:0 ptbd[3:0] port b data register bits ? for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port b pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r r r r r ptbdd3 ptbdd2 ptbdd1 ptbdd0 w reset00000000 figure 6-16. data direction for port b (ptbdd) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-7. ptbdd register field descriptions field description 3:0 ptbdd[3:0] data direction for port b bits ? these read/write bits control the direction of port b pins and what is read for ptbd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port b bit n and ptbd reads return the contents of ptbdn.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 93 6.7.4 port b pin control regi sters (ptbpe, ptbse, ptbds) in addition to the i/o control, port b pins are controlled by the registers listed below. 76543210 r r r r r ptbpe3 ptbpe2 ptbpe1 ptbpe0 w reset00000000 figure 6-17. internal pullup enable for port b (ptbpe) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-8. ptbpe register field descriptions field description 3:0 ptbpe[3:0] internal pullup enable for port b bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptb pin. for port b pins that are configured as outputs, thes e bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port b bit n. 1 internal pullup device enabled for port b bit n. 76543210 r r r r r ptbse3 ptbse2 ptbse1 ptbse0 w reset00000000 figure 6-18. output slew rate control enable (ptbse) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-9. ptbse register field descriptions field description 3:0 ptbse[3:0] output slew rate control enable for port b bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptb pin. for por t b pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port b bit n. 1 output slew rate control enabled for port b bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 94 freescale semiconductor 6.7.5 port c i/o registers (ptcd and ptcdd) port c parallel i/o function is cont rolled by the registers listed below. 76543210 r r r r r ptbds3 ptbds2 ptbds1 ptbds0 w reset00000000 figure 6-19. output drive strength selection for port b (ptbds) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-10. ptbds register field descriptions field description 3:0 ptbds[3:0] output drive strength selection for port b bits ? each of these control bits selects between low and high output drive for the associated ptb pin. 0 low output drive enabled for port b bit n. 1 high output drive enabled for port b bit n. 76543210 r0 r ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 w reset00000000 figure 6-20. port c data register (ptcd) 1 1 bit 6 is a reserved bit that must always be written to 0. table 6-11. ptcd register field descriptions field description 5:0 ptcd[5:0] port c data register bits ? for port c pins that are inputs, reads retu rn the logic level on the pin. for port c pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port c pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 95 6.7.6 port c pin control regi sters (ptcpe, ptcse, ptcds) in addition to the i/o control, port c pins are controlled by the registers listed below. 76543210 r0 r ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 w reset00000000 figure 6-21. data direction for port c (ptcdd) 1 1 bit 6 is a reserved bit that must always be written to 0. table 6-12. ptcdd regist er field descriptions field description 5:0 ptcdd[5:0] data direction for port c bits ? these read/write bits control the direction of port c pins and what is read for ptcd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port c bit n and ptcd reads return the contents of ptcdn. 76543210 r0 r ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 w reset00000000 figure 6-22. internal pullup enable for port c (ptcpe) 1 1 bit 6 is a reserved bit that must always be written to 0. table 6-13. ptcpe register field descriptions field description 5:0 ptcpe[5:0] internal pullup enable for port c bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptc pin. for port c pins that are configured as ou tputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port c bit n. 1 internal pullup device enabled for port c bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 96 freescale semiconductor 76543210 r0 r ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 w reset00000000 figure 6-23. output slew rate control enable for port c (ptcse) 1 1 bit 6 is a reserved bit that must always be written to 0. table 6-14. ptcse register field descriptions field description 5:0 ptcse[5:0] output slew rate control enable for port c bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptc pin. for po rt c pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port c bit n. 1 output slew rate control enabled for port c bit n. 76543210 r0 r ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 w reset00000000 figure 6-24. output drive strength selection for port c (ptcds) 1 1 bit 6 is a reserved bit that must always be written to 0. table 6-15. ptcds register field descriptions field description 5:0 ptcds[5:0] output drive strength selection for port c bits ? each of these control bits selects between low and high output drive for the associated ptc pin. 0 low output drive enabled for port c bit n. 1 high output drive enabled for port c bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 97 6.7.7 port d i/o registers (ptdd and ptddd) port d parallel i/o function is cont rolled by the registers listed below. 76543210 r r r r r ptdd3 ptdd2 ptdd1 ptdd0 w reset00000000 figure 6-25. port d data register (ptdd) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-16. ptdd register field descriptions field description 3:0 ptdd[3:0] port d data register bits ? for port d pins that are inputs, reads return the logic level on the pin. for port d pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port d pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptdd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r r r r r ptddd3 ptddd2 ptddd1 ptddd0 w reset00000000 figure 6-26. data direction for port d (ptddd) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-17. ptddd regist er field descriptions field description 3:0 ptddd[3:0] data direction for port d bits ? these read/write bits control the direction of port d pins and what is read for ptdd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port d bit n and ptdd reads return the contents of ptddn.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 98 freescale semiconductor 6.7.8 port d pin control regi sters (ptdpe, ptdse, ptdds) in addition to the i/o control, port d pins are controlled by the registers listed below. 76543210 r r r r r ptdpe3 ptdpe2 ptdpe1 ptdpe0 w reset00000000 figure 6-27. internal pullup enable for port d (ptdpe) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-18. ptdpe register field descriptions field description 3:0 ptdpe[3:0] internal pullup enable for port d bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptd pin. for port d pins that are configured as ou tputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port d bit n. 1 internal pullup device enabled for port d bit n. 76543210 r r r r r ptdse3 ptdse2 ptdse1 ptdse0 w reset00000000 figure 6-28. output slew rate control enable for port d (ptdse) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-19. ptdse register field descriptions field description 3:0 ptdse[3:0] output slew rate control enable for port d bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptd pin. for po rt d pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port d bit n. 1 output slew rate control enabled for port d bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 99 6.7.9 port e i/o registers (pted and ptedd) port e parallel i/o function is cont rolled by the registers listed below. 76543210 r r r r r ptdds3 ptdds2 ptdds1 ptdds0 w reset00000000 figure 6-29. output drive strength selection for port d (ptdds) 1 1 bits 7 through 4 are reserved bits that must always be written to 0. table 6-20. ptdds regi ster field descriptions field description 3:0 ptdds[3:0] output drive strength selection for port d bits ? each of these control bits selects between low and high output drive for the associated ptd pin. 0 low output drive enabled for port d bit n. 1 high output drive enabled for port d bit n. 76543210 r pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 w reset00000000 figure 6-30. port e data register (pted) table 6-21. pted register field descriptions field description 7:0 pted[7:0] port e data register bits ? for port e pins that are inputs, reads return the logic level on the pin. for port e pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port e pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces pted to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 100 freescale semiconductor 6.7.10 port e pin control regi sters (ptepe, ptese, pteds) in addition to the i/o control, port e pins are controlled by the registers listed below. 76543210 r ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 w reset00000000 figure 6-31. data direction for port e (ptedd) table 6-22. ptedd register field descriptions field description 7:0 ptedd[7:0] data direction for port e bits ? these read/write bits control the direct ion of port e pins and what is read for pted reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port e bit n and pted reads return the contents of ptedn. 76543210 r ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 w reset00000000 figure 6-32. internal pullup enable for port e (ptepe) table 6-23. ptepe register field descriptions field description 7:0 ptepe[7:0] internal pullup enable for port e bits ? each of these control bits determines if the internal pullup device is enabled for the associated pte pin. for port e pins that are configured as outputs, thes e bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port e bit n. 1 internal pullup device enabled for port e bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 101 76543210 r ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 w reset00000000 figure 6-33. output slew rate control enable for port e (ptese) table 6-24. ptese register field descriptions field description 7:0 ptese[7:0] output slew rate control enable for port e bits ? each of these control bits determine whether output slew rate control is enabled for the associated pte pin. for por t e pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port e bit n. 1 output slew rate control enabled for port e bit n. 76543210 r pteds7 pteds6 pteds5 pteds4 pteds3 pteds2 pteds1 pteds0 w reset00000000 figure 6-34. output drive strength selection for port e (pteds) table 6-25. pteds register field descriptions field description 7:0 pteds[7:0] output drive strength selection for port e bits ? each of these control bits selects between low and high output drive for the associated pte pin. 0 low output drive enabled for port e bit n. 1 high output drive enabled for port e bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 102 freescale semiconductor 6.7.11 port f i/o registers (ptfd and ptfdd) port f parallel i/o function is cont rolled by the registers listed below. 76543210 r r ptfd6 ptfd5 ptfd4 r r ptfd1 ptfd0 w reset00000000 figure 6-35. port f data register (ptfd) 1 1 bits 7, 3 and 2 are reserved bits that must always be written to 0. table 6-26. ptfd register field descriptions field description 6:4, 1:0 ptfdn port f data register bits ? for port f pins that are inputs, reads return the logic level on the pin. for port f pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port f pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptfd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r r ptfdd6 ptfdd5 ptfdd4 r r ptfdd1 ptfdd0 w reset00000000 figure 6-36. data direction for port f (ptfdd) 1 1 bits 7, 3 and 2 are reserved bits that must always be written to 0. table 6-27. ptfdd register field descriptions field description 6:4, 1:0 ptfddn data direction for port f bits ? these read/write bits control the directio n of port f pins and what is read for ptfd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port f bit n and ptfd reads return the contents of ptfdn.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 103 6.7.12 port f pin control registers (ptfpe, ptfse, ptfds) in addition to the i/o control, port f pins are controlled by the registers listed below. 76543210 r r ptfpe6 ptfpe5 ptfpe4 r r ptfpe1 ptfpe0 w reset00000000 figure 6-37. internal pullup enable for port f (ptfpe) 1 1 bits 7, 3 and 2 are reserved bits that must always be written to 0. table 6-28. ptfpe register field descriptions field description 6:4, 1:0 ptfpen internal pullup enable for port f bits ? each of these control bits determi nes if the internal pullup device is enabled for the associated ptf pin. for port f pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port f bit n. 1 internal pullup device enabled for port f bit n. 76543210 r r ptfse6 ptfse5 ptfse4 r r ptfse1 ptfse0 w reset00000000 figure 6-38. output slew rate control enable for port f (ptfse) 1 1 bits 7, 3 and 2 are reserved bits that must always be written to 0. table 6-29. ptfse register field descriptions field description 6:4, 1:0 ptfsen output slew rate control enable for port f bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptf pin. for port f pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port f bit n. 1 output slew rate control enabled for port f bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 104 freescale semiconductor 6.7.13 port g i/o registers (ptgd and ptgdd) port g parallel i/o function is cont rolled by the registers listed below. 76543210 r r ptfds6 ptfds5 ptfds4 r r ptfds1 ptfds0 w reset00000000 figure 6-39. output drive strength selection for port f (ptfds) 1 1 bits 7, 3 and 2 are reserved bits that must always be written to 0. table 6-30. ptfds register field descriptions field description 6:4, 1:0 ptfdsn output drive strength selection for port f bits ? each of these control bits selects between low and high output drive for the associated ptf pin. 0 low output drive enabled for port f bit n. 1 high output drive enabled for port f bit n. 76543210 r0 ptgd6 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 w reset00000000 figure 6-40. port g data register (ptgd) table 6-31. ptgd register field descriptions field description 6:0 ptgd[6:0] port g data register bits ? for port g pins that are inputs, reads return the logic level on the pin. for port g pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port g pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptgd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 105 6.7.14 port g pin control regi sters (ptgpe, ptgse, ptgds) in addition to the i/o control, port g pins are controlled by the registers listed below. 76543210 r0 ptgdd6 ptgdd5 ptgdd4 ptg dd3 ptgdd2 ptgdd1 ptgdd0 w reset00000000 figure 6-41. data direction for port g (ptgdd) table 6-32. ptgdd register field descriptions field description 6:0 ptgdd[6:0] data direction for port g bits ? these read/write bits control the directio n of port g pins and what is read for ptgd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port g bit n and ptgd reads return the contents of ptgdn. 76543210 r0 ptgpe6 ptgpe5 ptgpe4 ptg pe3 ptgpe2 ptgpe1 ptgpe0 w reset00000000 figure 6-42. internal pullup enable for port g bits (ptgpe) table 6-33. ptgpe register field descriptions field description 6:0 ptgpe[6:0] internal pullup enable for port g bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptg pin. for port g pins that ar e configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port g bit n. 1 internal pullup device enabled for port g bit n.
chapter 6 parallel input/output mc9s08ac16 series data sheet, rev. 8 106 freescale semiconductor 76543210 r0 ptgse6 ptgse5 ptgse4 ptg se3 ptgse2 ptgse1 ptgse0 w reset00000000 figure 6-43. output slew rate control enable for port g bits (ptgse) table 6-34. ptgse register field descriptions field description 6:0 ptgse[6:0] output slew rate control enable for port g bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptg pin. for port g pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port g bit n. 1 output slew rate control enabled for port g bit n. 76543210 r0 ptgds6 ptgds5 ptgds4 ptgd s3 ptgds2 ptgds1 ptgds0 w reset00000000 figure 6-44. output drive strengt h selection for port g (ptgds) table 6-35. ptgds register field descriptions field description 6:0 ptgds[6:0] output drive strength selection for port g bits ? each of these control bits selects between low and high output drive for the associated ptg pin. 0 low output drive enabled for port g bit n. 1 high output drive enabled for port g bit n.
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 107 chapter 7 central processor unit (s08cpuv2) 7.1 introduction this section provides summary information about the re gisters, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1 . the hcs08 cpu is fully source- and object-code -compatible with the m68hc08 cpu. several instructions and enhanced addressi ng modes were added to improve c compiler efficiency and to support a new background debug system which replaces the m onitor mode of earlier m68hc08 microcontrollers (mcu). 7.1.1 features features of the hcs08 cpu include: ? object code fully upward-compatible with m68hc05 a nd m68hc08 families ? all registers and memory are mappe d to a single 64-kbyte address space ? 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) ? 16-bit index register (h:x) with powerful indexed addressing modes ? 8-bit accumulator (a) ? many instructions treat x as a second general-purpose 8-bit register ? seven addressing modes: ? inherent ? operands in internal registers ? relative ? 8-bit signed offs et to branch destination ? immediate ? operand in next object code byte(s) ? direct ? operand in memory at 0x0000?0x00ff ? extended ? operand anywhere in 64-kbyte address space ? indexed relative to h:x ? five submodes including auto increment ? indexed relative to sp ? impr oves c efficiency dramatically ? memory-to-memory data move instructions with four address mode combinations ? overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ? efficient bit manipulation instructions ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? stop and wait instructions to invoke low-power operating modes
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 108 freescale semiconductor 7.2 programmer?s model and cpu registers figure 7-1 shows the five cpu registers. cpu regi sters are not part of the memory map. figure 7-1. cpu registers 7.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit regist er. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu re sults are often stored into the a accumulator after arithmetic and logical ope rations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data co mes from, or the contents of a can be stored to memory using various addressing m odes to specify the address where data from a will be stored. reset has no effect on the c ontents of the a accumulator. 7.2.2 index register (h:x) this 16-bit register is actually two se parate 8-bit regist ers (h and x), which often work together as a 16-bit address pointer where h holds the upp er byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc 05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8- bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, co mplemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or tr ansferred to a where arithm etic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is fo rced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 109 7.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available locati on on the automatic last-in-first-out (lifo) stack. the stack may be lo cated anywhere in the 64-kbyte a ddress space that has ram and can be any size up to the amount of available ram. the stac k is used to automaticall y save the return address for subroutine calls, the return address and cpu regi sters during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate valu e to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc 05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ra m (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was includ ed for compatibility with the m68hc05 family and is seldom used in new hcs08 progr ams because it only affects the low- order half of the stack pointer. 7.2.4 program counter (pc) the program counter is a 16-bit register that contai ns the address of the next instruction or operand to be fetched. during normal program execution, the pr ogram counter automatically increments to the next sequential memory location every time an in struction or operand is fetched. ju mp, branch, interrupt, and return operations load the program counter with an address ot her than that of the next sequential location. this is called a change-of-flow. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the first in struction that will be execu ted after exiting the reset state. 7.2.5 condition code register (ccr) the 8-bit condition code register contai ns the interrupt mask (i) and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set pe rmanently to 1. the following paragraphs describe the functions of the condition code bits in general term s. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1 . figure 7-2. condition code register condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow 70 ccr c v11hinz
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 110 freescale semiconductor 7.3 addressing modes addressing modes define the way th e cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/out put (i/o) ports share a single 64-kbyt e linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access va riables in ram can also be used to acce ss i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, m ove instructions use one addressing mode to specify the source operand and a second addressing mode to sp ecify the destination address. instructions such as brclr, brset, cbeq, and db nz use one addressing mode to specify the location table 7-1. ccr register field descriptions field description 7 v two?s complement overflow flag ? the cpu sets the overflow flag when a two?s complement overflow occurs. the signed branch instructions bgt, bg e, ble, and blt use the overflow flag. 0 no overflow 1overflow 4 h half-carry flag ? the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operati on. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction us es the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ? when the interrupt mask is set, all maska ble cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers ar e saved on the stack, but before the firs t instruction of the interrupt service routine is executed. interrupts are not recognized at the inst ruction boundary after any instruction that clears i (cli or tap). this ensures that the next instru ction after a cli or tap will always be execut ed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ? the cpu sets the negative flag when an arit hmetic operation, logi c operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most significant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ? the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1zero result 0 c carry/borrow flag ? the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation require s a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 0 no carry out of bit 7 1 carry out of bit 7
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 111 of an operand for a test and then use relative addres sing mode to specify the branch destination address when the tested condition is true . for brclr, brset, cbeq, and dbnz , the addressing mode listed in the instruction set tables is the addressing mode need ed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination locatio n for branch instructions. a signed 8-bit offset value is located in the memory location immediate ly following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 immediate addressing mode (imm) in immediate addressing mode, the op erand needed to complete the inst ruction is included in the object code immediately followi ng the instruction opcode in memory. in the case of a 16-bi t immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memo ry location after that. 7.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the lo w-order eight bits of an address in the direct page (0x0000?0x00ff). during execution a 16-bit address is formed by concatenati ng an implied 0x00 for the high-order half of the address and th e direct address from the instruct ion to get the 16-bit address where the desired operand is located. this is faster and more memory efficien t than specifying a complete 16-bit address for the operand. 7.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 indexed addressing mode indexed addressing mode has seven variations including five that use the 16-bit h:x index register pair and two that use the stack po inter as the base reference.
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 112 freescale semiconductor 7.3.6.1 indexed, no offset (ix) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. 7.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit va lue in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 special operations the cpu performs a few special opera tions that are similar to instruct ions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop a nd wait directly affect other mcu circuitry. this section provides additional informat ion about these operations.
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 113 7.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an ex ternal active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determin es the source, refer to the resets, interrupts, and system configuration chapter. the reset event is considered conc luded when the sequence to determin e whether the reset came from an internal source is done and when the reset pin is no longer asse rted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0x fffe and 0xffff and to fill the instruction queue in preparation for exec ution of the first program instruction. 7.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instructi on, except the address used for the vector fetch is determined by the highest priority in terrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program info rmation starting at the address i ndicated by the interrupt vector to fill the instruction queue in preparation for ex ecution of the first instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routin e. although it is possible to clear th e i bit with an instruction in the interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are di fficult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the hi gh-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt se quence. the user must use a pshh instruction at the beginning of the service routine to save h and then us e a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certa in that the interr upt service routine does not use any instructions or auto-increment addressing modes th at might change the value of h. the software interrupt (swi) instruction is like a ha rdware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within th e program so it is not asynchronous to program execution.
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 114 freescale semiconductor 7.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumpt ion while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event oc curs, the cpu clocks will resume and the interrupt or reset even t will be processed normally. if a serial background comma nd is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu cloc ks will resume and th e cpu will enter activ e background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu ev en if it is in wait mode. 7.4.4 stop mode operation usually, all system clocks, includi ng the crystal oscillator (when used ), are halted during stop mode to minimize power consumption. in such sy stems, external circui try is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be configured to keep a minimum set of clocks running in stop mode. this op tionally allows an internal periodi c signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the b ackground interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial back ground command is issued to the mc u through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial backgr ound commands can be processed. this en sures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode de pends on the particular hcs08 and whether the osc illator was stopped in stop mode. refer to the modes of operation chapter for more details. 7.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compar ed to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to st op processing user instructions and enter the active background mode. the only way to re sume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program re aches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program.
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 115 7.5 hcs08 instruction set summary table 7-2 provides a summary of the hcs08 instruction se t in all possible addressing modes. the table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode vari ation of each instruction. table 7-2. . instruction set summary (sheet 1 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c adc # opr8i adc opr8a adc opr16a adc oprx16 ,x adc oprx8 ,x adc ,x adc oprx16 ,sp adc oprx8 ,sp add with carry a (a) + (m) + (c) imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9e d9 9e e9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 1 1 ? add # opr8i add opr8a add opr16a add oprx16 ,x add oprx8 ,x add ,x add oprx16 ,sp add oprx8 ,sp add without carry a (a) + (m) imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9e db 9e eb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 1 1 ? ais # opr8i add immediate value (signed) to stack pointer sp (sp) + (m) imm a7 ii 2 pp ? 1 1 ? ? ? ? ? aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) imm af ii 2 pp ? 1 1 ? ? ? ? ? and # opr8i and opr8a and opr16a and oprx16 ,x and oprx8 ,x and ,x and oprx16 ,sp and oprx8 ,sp logical and a (a) & (m) imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9e d4 9e e4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 ? ? ? asl opr8a asla aslx asl oprx8 ,x asl ,x asl oprx8 ,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? asr opr8a asra asrx asr oprx8 ,x asr ,x asr oprx8 ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e 67 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ? ? c b0 b7 0 b0 b7 c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 116 freescale semiconductor bcc rel branch if carry bit clear (if c = 0) rel 24 rr 3 ppp ? 1 1 ? ? ? ? ? bclr n , opr8a clear bit n in memory (mn 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ? 1 1 ? ? ? ? ? bcs rel branch if carry bit set (if c = 1) (same as blo) rel 25 rr 3 ppp ? 1 1 ? ? ? ? ? beq rel branch if equal (if z = 1) rel 27 rr 3 ppp ? 1 1 ? ? ? ? ? bge rel branch if greater than or equal to (if n v = 0) (signed) rel 90 rr 3 ppp ? 1 1 ? ? ? ? ? bgnd enter active background if enbdm=1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ fp...ppp ? 1 1 ? ? ? ? ? bgt rel branch if greater than (if z | (n v) = 0) (signed) rel 92 rr 3 ppp ? 1 1 ? ? ? ? ? bhcc rel branch if half carry bit clear (if h = 0) rel 28 rr 3 ppp ? 1 1 ? ? ? ? ? bhcs rel branch if half carry bit set (if h = 1) rel 29 rr 3 ppp ? 1 1 ? ? ? ? ? bhi rel branch if higher (if c | z = 0) rel 22 rr 3 ppp ? 1 1 ? ? ? ? ? bhs rel branch if higher or same (if c = 0) (same as bcc) rel 24 rr 3 ppp ? 1 1 ? ? ? ? ? bih rel branch if irq pin high (if irq pin = 1) rel 2f rr 3 ppp ? 1 1 ? ? ? ? ? bil rel branch if irq pin low (if irq pin = 0) rel 2e rr 3 ppp ? 1 1 ? ? ? ? ? bit # opr8i bit opr8a bit opr16a bit oprx16 ,x bit oprx8 ,x bit ,x bit oprx16 ,sp bit oprx8 ,sp bit test (a) & (m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9e d5 9e e5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 ? ? ? ble rel branch if less than or equal to (if z | (n v) = 1) (signed) rel 93 rr 3 ppp ? 1 1 ? ? ? ? ? blo rel branch if lower (if c = 1) (same as bcs) rel 25 rr 3 ppp ? 1 1 ? ? ? ? ? bls rel branch if lower or same (if c | z = 1) rel 23 rr 3 ppp ? 1 1 ? ? ? ? ? blt rel branch if less than (if n v = 1) (signed) rel 91 rr 3 ppp ? 1 1 ? ? ? ? ? bmc rel branch if interrupt mask clear (if i = 0) rel 2c rr 3 ppp ? 1 1 ? ? ? ? ? bmi rel branch if minus (if n = 1) rel 2b rr 3 ppp ? 1 1 ? ? ? ? ? bms rel branch if interrupt mask set (if i = 1) rel 2d rr 3 ppp ? 1 1 ? ? ? ? ? bne rel branch if not equal (if z = 0) rel 26 rr 3 ppp ? 1 1 ? ? ? ? ? table 7-2. . instruction set summary (sheet 2 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 117 bpl rel branch if plus (if n = 0) rel 2a rr 3 ppp ? 1 1 ? ? ? ? ? bra rel branch always (if i = 1) rel 20 rr 3 ppp ? 1 1 ? ? ? ? ? brclr n , opr8a , rel branch if bit n in memory clear (if (mn) = 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ? 1 1 ? ? ? ? brn rel branch never (if i = 0) rel 21 rr 3 ppp ? 1 1 ? ? ? ? ? brset n , opr8a , rel branch if bit n in memory set (if (mn) = 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ? 1 1 ? ? ? ? bset n , opr8a set bit n in memory (mn 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ? 1 1 ? ? ? ? ? bsr rel branch to subroutine pc (pc) + $0002 push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 pc (pc) + rel rel ad rr 5 ssppp ? 1 1 ? ? ? ? ? cbeq opr8a , rel cbeqa # opr8i , rel cbeqx # opr8i , rel cbeq oprx8 ,x+, rel cbeq ,x+, rel cbeq oprx8 ,sp, rel compare and... branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e 61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 rpppp pppp pppp rpppp rfppp prpppp ? 1 1 ? ? ? ? ? clc clear carry bit (c 0) inh 98 1 p ? 1 1 ? ? ? ? 0 cli clear interrupt mask bit (i 0) inh 9a 1 p ? 1 1 ? 0 ? ? ? clr opr8a clra clrx clrh clr oprx8 ,x clr ,x clr oprx8 ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e 6f dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 0 1 1 ? ? 0 1 ? table 7-2. . instruction set summary (sheet 3 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 118 freescale semiconductor cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8 ,sp compare accumulator with memory a ? m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9e d1 9e e1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 1 1 ?? com opr8a coma comx com oprx8 ,x com ,x com oprx8 ,sp complement m (m )= $ff ? (m) (one?s complement) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) dir inh inh ix1 ix sp1 33 43 53 63 73 9e 63 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 0 1 1 ? ? 1 cphx opr16a cphx # opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ? (m:m + $0001) (ccr updated but operands not changed) ext imm dir sp1 3e 65 75 9e f3 hh ll jj kk dd ff 6 3 5 6 prrfpp ppp rrfpp prrfpp 1 1 ?? cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8 ,x cpx ,x cpx oprx16 ,sp cpx oprx8 ,sp compare x (index register low) with memory x ? m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9e d3 9e e3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 1 1 ?? daa decimal adjust accumulator after add or adc of bcd values inh 72 1 p u 1 1 ? ? dbnz opr8a , rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp, rel decrement a, x, or m and branch if not zero (if (result) 0) dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e 6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 rfwpppp fppp fppp rfwpppp rfwppp prfwpppp ? 1 1 ? ? ? ? ? dec opr8a deca decx dec oprx8 ,x dec ,x dec oprx8 ,sp decrement m (m) ? $01 a (a) ? $01 x (x) ? $01 m (m) ? $01 m (m) ? $01 m (m) ? $01 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e 6a dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? ? div divide a (h:a) (x); h remainder inh 52 6 fffffp ? 1 1 ? ? ? eor # opr8i eor opr8a eor opr16a eor oprx16 ,x eor oprx8 ,x eor ,x eor oprx16 ,sp eor oprx8 ,sp exclusive or memory with accumulator a (a m) imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9e d8 9e e8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 ? ? ? table 7-2. . instruction set summary (sheet 4 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 119 inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + $01 a (a) + $01 x (x) + $01 m (m) + $01 m (m) + $01 m (m) + $01 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e 6c dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ? ? ? jmp opr8a jmp opr16a jmp oprx16 ,x jmp oprx8 ,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 ppp pppp pppp ppp ppp ? 1 1 ? ? ? ? ? jsr opr8a jsr opr16a jsr oprx16 ,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 ssppp pssppp pssppp ssppp ssppp ? 1 1 ? ? ? ? ? lda # opr8i lda opr8a lda opr16a lda oprx16 ,x lda oprx8 ,x lda ,x lda oprx16 ,sp lda oprx8 ,sp load accumulator from memory a (m) imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9e d6 9e e6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 ? ? ? ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16 ,x ldhx oprx8 ,x ldhx oprx8 ,sp load index register (h:x) h:x ( m:m + $0001 ) imm dir ext ix ix2 ix1 sp1 45 55 32 9e ae 9e be 9e ce 9e fe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 ppp rrpp prrpp prrfp pprrpp prrpp prrpp 0 1 1 ? ? ? ldx # opr8i ldx opr8a ldx opr16a ldx oprx16 ,x ldx oprx8 ,x ldx ,x ldx oprx16 ,sp ldx oprx8 ,sp load x (index register low) from memory x (m) imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9e de 9e ee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 ? ? ? lsl opr8a lsla lslx lsl oprx8 ,x lsl ,x lsl oprx8 ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? lsr opr8a lsra lsr x lsr oprx8 ,x lsr ,x lsr oprx8 ,sp logical shift right dir inh inh ix1 ix sp1 34 44 54 64 74 9e 64 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? 0 table 7-2. . instruction set summary (sheet 5 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c c b0 b7 0 b0 b7 c 0
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 120 freescale semiconductor mov opr8a , opr8a mov opr8a ,x+ mov # opr8i , opr8a mov ,x+, opr8a move (m) destination (m) source in ix+/dir and dir/ix+ modes, h:x (h:x) + $0001 dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 rpwpp rfwpp pwpp rfwpp 0 1 1 ? ? ? mul unsigned multiply x:a (x) (a) inh 42 5 ffffp ? 1 1 0? ? ? 0 neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate m ? (m) = $00 ? (m) (two?s complement) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e 60 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? nop no operation ? uses 1 bus cycle inh 9d 1 p ? 1 1 ? ? ? ? ? nsa nibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 p ? 1 1 ? ? ? ? ? ora # opr8i ora opr8a ora opr16a ora oprx16 ,x ora oprx8 ,x ora ,x ora oprx16 ,sp ora oprx8 ,sp inclusive or accumulator and memory a (a) | (m) imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9e da 9e ea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 ? ? ? psha push accumulator onto stack push (a); sp (sp) ? $0001 inh 87 2 sp ? 1 1 ? ? ? ? ? pshh push h (index register high) onto stack push (h); sp (sp) ? $0001 inh 8b 2 sp ? 1 1 ? ? ? ? ? pshx push x (index register low) onto stack push (x); sp (sp) ? $0001 inh 89 2 sp ? 1 1 ? ? ? ? ? pula pull accumulator from stack sp (sp + $0001); pull ( a ) inh 86 3 ufp ? 1 1 ? ? ? ? ? pulh pull h (index register high) from stack sp (sp + $0001); pull ( h ) inh 8a 3 ufp ? 1 1 ? ? ? ? ? pulx pull x (index register low) from stack sp (sp + $0001); pull ( x ) inh 88 3 ufp ? 1 1 ? ? ? ? ? rol opr8a rola rolx rol oprx8 ,x rol ,x rol oprx8 ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e 69 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e 66 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 ?? table 7-2. . instruction set summary (sheet 6 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c c b0 b7 b0 b7 c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 121 rsp reset stack pointer (low byte) spl $ff (high byte not affected) inh 9c 1 p ? 1 1 ? ? ? ? ? rti return from interrupt sp (sp) + $0001; pull (ccr) sp (sp) + $0001; pull (a) sp (sp) + $0001; pull (x) sp (sp) + $0001; pull (pch) sp (sp) + $0001; pull (pcl) inh 80 9 uuuuufppp 1 1 rts return from subroutine sp sp + $0001 ; pull ( pch) sp sp + $0001; pull (pcl) inh 81 5 ufppp ? 1 1 ? ? ? ? ? sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8 ,x sbc ,x sbc oprx16 ,sp sbc oprx8 ,sp subtract with carry a (a) ? (m) ? (c) imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9e d2 9e e2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 1 1 ?? sec set carry bit (c 1) inh 99 1 p ? 1 1 ? ? ? ? 1 sei set interrupt mask bit (i 1) inh 9b 1 p ? 1 1 ? 1 ? ? ? sta opr8a sta opr16a sta oprx16 ,x sta oprx8 ,x sta ,x sta oprx16 ,sp sta oprx8 ,sp store accumulator in memory m (a) dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9e d7 9e e7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 0 1 1 ? ? ? sthx opr8a sthx opr16a sthx oprx8 ,sp store h:x (index reg.) (m:m + $0001) (h:x) dir ext sp1 35 96 9e ff dd hh ll ff 4 5 5 wwpp pwwpp pwwpp 0 1 1 ? ? ? stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing inh 8e 2 fp... ? 1 1 ? 0 ? ? ? stx opr8a stx opr16a stx oprx16 ,x stx oprx8 ,x stx ,x stx oprx16 ,sp stx oprx8 ,sp store x (low 8 bits of index register) in memory m (x) dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9e df 9e ef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 0 1 1 ? ? ? table 7-2. . instruction set summary (sheet 7 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 122 freescale semiconductor sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8 ,x sub ,x sub oprx16 ,sp sub oprx8 ,sp subtract a (a) ? (m) imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9e d0 9e e0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 1 1 ?? swi software interrupt pc (pc) + $0001 push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 push (x); sp (sp) ? $0001 push (a); sp (sp) ? $0001 push (ccr); sp (sp) ? $0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte inh 83 11 sssssvvfppp ? 1 1 ? 1 ? ? ? tap transfer accumulator to ccr ccr (a) inh 84 1 p 1 1 tax transfer accumulator to x (index register low) x (a) inh 97 1 p ? 1 1 ? ? ? ? ? tpa transfer ccr to accumulator a (ccr) inh 85 1 p ? 1 1 ? ? ? ? ? tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ? $00 (a) ? $00 (x) ? $00 (m) ? $00 (m) ? $00 (m) ? $00 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e 6d dd ff ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 0 1 1 ? ? ? tsx transfer sp to index reg. h:x (sp) + $0001 inh 95 2 fp ? 1 1 ? ? ? ? ? txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 p ? 1 1 ? ? ? ? ? table 7-2. . instruction set summary (sheet 8 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 123 txs transfer index reg. to sp sp (h:x) ? $0001 inh 94 2 fp ? 1 1 ? ? ? ? ? wait enable interrupts; wait for interrupt i bit 0; halt cpu inh 8f 2+ fp... ? 1 1 ? 0 ? ? ? source form: everything in the source forms columns, except expressions in italic characters , is literal information which must appear in the assembly source file exactly as shown. the initial 3- to 5-letter mnemonic and t he characters (# , ( ) and +) are always a lite ral characters. n any label or expression that evaluates to a single integer in the range 0-7. opr8i any label or expression that evaluates to an 8-bit immediate value. opr16i any label or expression that evaluates to a 16-bit immediate value. opr8a any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a any label or expression that evaluates to a 16-bit address. oprx8 any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel any label or expression that refers to an address that is within ?128 to +127 locations from the start of the next instruction. operation symbols: a accumulator ccr condition code register h index register high byte m memory location n any bit opr operand (one or two bytes) pc program counter pch program counter high byte pcl program counter low byte rel relative program counter offset byte sp stack pointer spl stack pointer low byte x index register low byte & logical and | logical or logical exclusive or ( ) contents of + add ? subtract, negation (two?s complement) multiply divide # immediate value loaded with : concatenated with addressing modes: dir direct addressing mode ext extended addressing mode imm immediate addressing mode inh inherent addressing mode ix indexed, no offset addressing mode ix1 indexed, 8-bit offset addressing mode ix2 indexed, 16-bit offset addressing mode ix+ indexed, no offset, post increment addressing mode ix1+ indexed, 8-bit offset, post increment addressing mode rel relative addressing mode sp1 stack pointer, 8-bit offset addressing mode sp2 stack pointer 16-bit offset addressing mode cycle-by-cycle codes: f free cycle. this indicates a cycle where the cpu does not require use of the system buses. an f cycle is always one cycle of the system bus clock and is always a read cycle. p progryam fetch; read from next consecutive location in program memory r read 8-bit operand s push (write) one byte onto stack u pop (read) one byte from stack v read vector from $ffxx (high byte first) w write 8-bit operand ccr bits: voverflow bit h half-carry bit i interrupt mask n negative bit z zero bit c carry/borrow bit ccr effects: set or cleared ? not affected u undefined table 7-2. . instruction set summary (sheet 9 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 hi n z c
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 124 freescale semiconductor table 7-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modi fy-write control register/memory 00 5 brset0 3dir 10 5 bset0 2dir 20 3 bra 2rel 30 5 neg 2dir 40 1 nega 1inh 50 1 negx 1inh 60 5 neg 2ix1 70 4 neg 1ix 80 9 rti 1inh 90 3 bge 2rel a0 2 sub 2imm b0 3 sub 2dir c0 4 sub 3 ext d0 4 sub 3ix2 e0 3 sub 2ix1 f0 3 sub 1ix 01 5 brclr0 3dir 11 5 bclr0 2dir 21 3 brn 2rel 31 5 cbeq 3dir 41 4 cbeqa 3imm 51 4 cbeqx 3imm 61 5 cbeq 3ix1+ 71 5 cbeq 2ix+ 81 6 rts 1inh 91 3 blt 2rel a1 2 cmp 2imm b1 3 cmp 2dir c1 4 cmp 3 ext d1 4 cmp 3ix2 e1 3 cmp 2ix1 f1 3 cmp 1ix 02 5 brset1 3dir 12 5 bset1 2dir 22 3 bhi 2rel 32 5 ldhx 3ext 42 5 mul 1inh 52 6 div 1inh 62 1 nsa 1inh 72 1 daa 1inh 82 5+ bgnd 1inh 92 3 bgt 2rel a2 2 sbc 2imm b2 3 sbc 2dir c2 4 sbc 3 ext d2 4 sbc 3ix2 e2 3 sbc 2ix1 f2 3 sbc 1ix 03 5 brclr1 3dir 13 5 bclr1 2dir 23 3 bls 2rel 33 5 com 2dir 43 1 coma 1inh 53 1 comx 1inh 63 5 com 2ix1 73 4 com 1ix 83 11 swi 1inh 93 3 ble 2rel a3 2 cpx 2imm b3 3 cpx 2dir c3 4 cpx 3 ext d3 4 cpx 3ix2 e3 3 cpx 2ix1 f3 3 cpx 1ix 04 5 brset2 3dir 14 5 bset2 2dir 24 3 bcc 2rel 34 5 lsr 2dir 44 1 lsra 1inh 54 1 lsrx 1inh 64 5 lsr 2ix1 74 4 lsr 1ix 84 1 ta p 1inh 94 2 txs 1inh a4 2 and 2imm b4 3 and 2dir c4 4 and 3 ext d4 4 and 3ix2 e4 3 and 2ix1 f4 3 and 1ix 05 5 brclr2 3dir 15 5 bclr2 2dir 25 3 bcs 2rel 35 4 sthx 2dir 45 3 ldhx 3imm 55 4 ldhx 2dir 65 3 cphx 3imm 75 5 cphx 2dir 85 1 tpa 1inh 95 2 tsx 1inh a5 2 bit 2imm b5 3 bit 2dir c5 4 bit 3 ext d5 4 bit 3ix2 e5 3 bit 2ix1 f5 3 bit 1ix 06 5 brset3 3dir 16 5 bset3 2dir 26 3 bne 2rel 36 5 ror 2dir 46 1 rora 1inh 56 1 rorx 1inh 66 5 ror 2ix1 76 4 ror 1ix 86 3 pula 1inh 96 5 sthx 3ext a6 2 lda 2imm b6 3 lda 2dir c6 4 lda 3 ext d6 4 lda 3ix2 e6 3 lda 2ix1 f6 3 lda 1ix 07 5 brclr3 3dir 17 5 bclr3 2dir 27 3 beq 2rel 37 5 asr 2dir 47 1 asra 1inh 57 1 asrx 1inh 67 5 asr 2ix1 77 4 asr 1ix 87 2 psha 1inh 97 1 ta x 1inh a7 2 ais 2imm b7 3 sta 2dir c7 4 sta 3 ext d7 4 sta 3ix2 e7 3 sta 2ix1 f7 2 sta 1ix 08 5 brset4 3dir 18 5 bset4 2dir 28 3 bhcc 2rel 38 5 lsl 2dir 48 1 lsla 1inh 58 1 lslx 1inh 68 5 lsl 2ix1 78 4 lsl 1ix 88 3 pulx 1inh 98 1 clc 1inh a8 2 eor 2imm b8 3 eor 2dir c8 4 eor 3 ext d8 4 eor 3ix2 e8 3 eor 2ix1 f8 3 eor 1ix 09 5 brclr4 3dir 19 5 bclr4 2dir 29 3 bhcs 2rel 39 5 rol 2dir 49 1 rola 1inh 59 1 rolx 1inh 69 5 rol 2ix1 79 4 rol 1ix 89 2 pshx 1inh 99 1 sec 1inh a9 2 adc 2imm b9 3 adc 2dir c9 4 adc 3 ext d9 4 adc 3ix2 e9 3 adc 2ix1 f9 3 adc 1ix 0a 5 brset5 3dir 1a 5 bset5 2dir 2a 3 bpl 2rel 3a 5 dec 2dir 4a 1 deca 1inh 5a 1 decx 1inh 6a 5 dec 2ix1 7a 4 dec 1ix 8a 3 pulh 1inh 9a 1 cli 1inh aa 2 ora 2imm ba 3 ora 2dir ca 4 ora 3 ext da 4 ora 3ix2 ea 3 ora 2ix1 fa 3 ora 1ix 0b 5 brclr5 3dir 1b 5 bclr5 2dir 2b 3 bmi 2rel 3b 7 dbnz 3dir 4b 4 dbnza 2inh 5b 4 dbnzx 2inh 6b 7 dbnz 3ix1 7b 6 dbnz 2ix 8b 2 pshh 1inh 9b 1 sei 1inh ab 2 add 2imm bb 3 add 2dir cb 4 add 3 ext db 4 add 3ix2 eb 3 add 2ix1 fb 3 add 1ix 0c 5 brset6 3dir 1c 5 bset6 2dir 2c 3 bmc 2rel 3c 5 inc 2dir 4c 1 inca 1inh 5c 1 incx 1inh 6c 5 inc 2ix1 7c 4 inc 1ix 8c 1 clrh 1inh 9c 1 rsp 1inh bc 3 jmp 2dir cc 4 jmp 3 ext dc 4 jmp 3ix2 ec 3 jmp 2ix1 fc 3 jmp 1ix 0d 5 brclr6 3dir 1d 5 bclr6 2dir 2d 3 bms 2rel 3d 4 tst 2dir 4d 1 tsta 1inh 5d 1 tstx 1inh 6d 4 tst 2ix1 7d 3 tst 1ix 9d 1 nop 1inh ad 5 bsr 2rel bd 5 jsr 2dir cd 6 jsr 3 ext dd 6 jsr 3ix2 ed 5 jsr 2ix1 fd 5 jsr 1ix 0e 5 brset7 3dir 1e 5 bset7 2dir 2e 3 bil 2rel 3e 6 cphx 3ext 4e 5 mov 3dd 5e 5 mov 2dix+ 6e 4 mov 3imd 7e 5 mov 2ix+d 8e 2+ stop 1inh 9e page 2 ae 2 ldx 2imm be 3 ldx 2dir ce 4 ldx 3 ext de 4 ldx 3ix2 ee 3 ldx 2ix1 fe 3 ldx 1ix 0f 5 brclr7 3dir 1f 5 bclr7 2dir 2f 3 bih 2rel 3f 5 clr 2dir 4f 1 clra 1inh 5f 1 clrx 1inh 6f 5 clr 2ix1 7f 4 clr 1ix 8f 2+ wait 1inh 9f 1 txa 1inh af 2 aix 2imm bf 3 stx 2dir cf 4 stx 3 ext df 4 stx 3ix2 ef 3 stx 2ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 125 bit-manipulation branch read-modi fy-write control register/memory 9e60 6 neg 3sp1 9ed0 5 sub 4sp2 9ee0 4 sub 3sp1 9e61 6 cbeq 4sp1 9ed1 5 cmp 4sp2 9ee1 4 cmp 3sp1 9ed2 5 sbc 4sp2 9ee2 4 sbc 3sp1 9e63 6 com 3sp1 9ed3 5 cpx 4sp2 9ee3 4 cpx 3sp1 9ef3 6 cphx 3sp1 9e64 6 lsr 3sp1 9ed4 5 and 4sp2 9ee4 4 and 3sp1 9ed5 5 bit 4sp2 9ee5 4 bit 3sp1 9e66 6 ror 3sp1 9ed6 5 lda 4sp2 9ee6 4 lda 3sp1 9e67 6 asr 3sp1 9ed7 5 sta 4sp2 9ee7 4 sta 3sp1 9e68 6 lsl 3sp1 9ed8 5 eor 4sp2 9ee8 4 eor 3sp1 9e69 6 rol 3sp1 9ed9 5 adc 4sp2 9ee9 4 adc 3sp1 9e6a 6 dec 3sp1 9eda 5 ora 4sp2 9eea 4 ora 3sp1 9e6b 8 dbnz 4sp1 9edb 5 add 4sp2 9eeb 4 add 3sp1 9e6c 6 inc 3sp1 9e6d 5 tst 3sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4ix2 9ece 5 ldhx 3ix1 9ede 5 ldx 4sp2 9eee 4 ldx 3sp1 9efe 5 ldhx 3sp1 9e6f 6 clr 3sp1 9edf 5 stx 4sp2 9eef 4 stx 3sp1 9eff 5 sthx 3sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3sp1 hcs08 cycles instruction mnemonic addressing mode table 7-3. opcode map (sheet 2 of 2)
chapter 7 central processor unit (s08cpuv2) mc9s08ac16 series data sheet, rev. 8 126 freescale semiconductor
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 127 chapter 8 internal clock generator (s08icgv4) the internal clock generation (icg) module is used to generate the system clocks for the mc9s08ac16 series mcu. the analog supply lines v dda and v ssa are internally derived from the mcu?s v dd and v ss pins. electrical parametric da ta for the icg may be found in appendix a, ?electrica l characteristics and timing specifications .? figure 8-1. system clock distribution diagram note freescale semiconductor recommends that flash location 0xffbe be reserved to store a nonvolatile ve rsion of icgtrm. this will allow debugger and programmer vendors to perform a manual trim operation and store the resultant icgtrm value for users to access at a later time. tpm1 tpm2 iic1 sci1 sci2 spi1 bdc cpu adc1 ram flash icg icgout 2 ffe system logic busclk icglclk* control xclk* icgerclk * icglclk is the alternate bdc clock source for the mc9s08ac16 series. * xclk is the fixed-frequency clock. 2 flash has frequency requirements for program and erase operation. see the electricals appendix. adc has min and max frequency requirements. see the electricals appendix and the adc chapter. tpm3 cop rti 1 khz tpmclk
chapter 8 internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 128 freescale semiconductor figure 8-2. mc9s08ac16 block diagram highlighting the icg ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 129 8.1 introduction the icg provides multiple options for clock sources. this offers a user great flexibility when making choices between cost, prec ision, current draw, and performance. as seen in figure 8-3 , the icg consists of four functional blocks. each of th ese is briefly described here and then in more detail in a later section. ? oscillator block ? the oscillator block provides means for connecting an external crystal or resonator. two frequency ranges are software sel ectable to allow optimal startup and stability. alternatively, the oscillator block ca n be used to route an external squa re wave to the system clock. external sources can provide a very precise cloc k source. the oscillator is capable of being configured for low power mode or hi gh amplitude mode as selected by hgo. ? internal reference generator ? the internal reference generator consists of two controlled clock sources. one is designed to be a pproximately 8 mhz and can be selected as a local clock for the background debug controller. the other internal re ference clock source is typically 243 khz and can be trimmed for finer accuracy via software when a precise ti med event is input to the mcu. this provides a highly reliable, low-cost clock source. ? frequency-locked loop ? a frequency-locked loop (fll) st age takes either the internal or external clock source and multiplies it to a higher freque ncy. status bits provi de information when the circuit has achieved lock and when it falls out of lock. additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. ? clock select block ? the clock select block provides se veral switch options for connecting different clock sources to the system clock tree. icgdclk is the multip lied clock frequency out of the fll, icgerclk is the reference clock fre quency from the crystal or external clock source, and ffe (fixed frequency enable) is a control si gnal used to control the system fixed frequency clock (xclk). icglclk is the clock source for the background debug controller (bdc). 8.1.1 features the module is intended to be very us er friendly with many of the featur es occurring automatically without user intervention. to quickly configure the module, go to section 8.5, ?initiali zation/application information ? and pick an example that best suits the application needs. features of the icg and clock distribution system: ? several options for the primary clock source allow a wide range of cost, frequency, and precision choices: ? 32 khz?100 khz crystal or resonator ? 1 mhz?16 mhz crystal or resonator ? external clock ? internal reference generator ? defaults to self-clocked mode to minimize startup delays ? frequency-locked loop (fll) generates 8 m hz to 40 mhz (for bus rates up to 20 mhz) ? uses external or internal clock as reference frequency ? automatic lockout of non-running clock sources ? reset or interrupt on loss of clock or loss of fll lock
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 130 freescale semiconductor ? digitally-controlled oscillator (dco) preserves previous fre quency settings, allowing fast frequency lock when re covering from stop3 mode ? dco will maintain operating frequency during a loss or removal of reference clock ? post-fll divider selects 1 of 8 bus rate divisors (/1 through /128) ? separate self-clocked s ource for real-time interrupt ? trimmable internal clock so urce supports sci communications without additional external components ? automatic fll engagement after lock is acquired ? external oscillator selectab le for low power or high gain 8.1.2 modes of operation this is a high-level description only. detailed descriptions of operating modes are contained in section 8.4, ?functional description .? ? mode 1 ? off the output clock, icgout, is static. this mode may be entered when the stop instruction is executed. ? mode 2 ? self-clocked (scm) default mode of operation that is entered immediately after reset. the icg?s fll is open loop and the digitally controlled oscillat or (dco) is free running at a frequency set by the filter bits. ? mode 3 ? fll engaged internal (fei) in this mode, the icg?s fll is used to create frequencies that are progr ammable multiples of the internal reference clock. ? fll engaged internal unlocked is a transition state that occurs while the fll is attempting to lock. the fll dco frequency is off target a nd the fll is adjusting the dco to match the target frequency. ? fll engaged internal locked is a state that occurs when the fll detects that the dco is locked to a multiple of the internal reference. ? mode 4 ? fll bypassed external (fbe) in this mode, the icg is configur ed to bypass the fll and use an ex ternal clock as the clock source. ? mode 5 ? fll engaged external (fee) the icg?s fll is used to generate frequencies that are programmable multiples of the external clock reference. ? fll engaged external unlocked is a transition state that occurs while the fll is attempting to lock. the fll dco frequency is off target a nd the fll is adjusting the dco to match the target frequency. ? fll engaged external locked is a state which occurs when the fll detects that the dco is locked to a multiple of the external reference.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 131 8.1.3 block diagram figure 8-3 is a top-level diagram that s hows the functional organization of the internal clock generation (icg) module. this section includes a ge neral description and a feature list. figure 8-3. icg block diagram 8.2 external signal description the oscillator pins are used to provi de an external clock source for the mcu. the oscillator pins are gain controlled in low-power mode (default). oscillat or amplitudes in low-power mode are limited to approximately 1 v, peak-to-peak. 8.2.1 extal ? external refere nce clock / oscillator input if upon the first write to icgc1, either the fee mode or fbe m ode is selected, this pi n functions as either the external clock input or the input of the oscillator circuit as dete rmined by refs. if upon the first write to icgc1, either the fei mode or scm mode is selected, this pin is not used by the icg. 8.2.2 xtal ? oscillator output if upon the first write to icgc1, either the fee mode or fbe mode is selected, this pin functions as the output of the oscillator circuit. if upon the first writ e to icgc1, either the fe i mode or scm mode is selected, this pin is not us ed by the icg. the oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. this mode of operation is selected by hgo = 1. oscillator (osc) frequency internal extal xtal reference generators clock select 8 mhz irg loss of lock and clock detector locked loop (fll) fixed clock select icgout typ 243 khz rg icglclk icg ffe v dda v ssa (see note 2) (see note 2) dco with external ref select ref select local clock for optional use with bdc output clock select icgdclk /r icgerclk icgirclk notes: 1 not all hcs08 microcontrollers have unique supply pins for the icg. see the device pin assignments.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 132 freescale semiconductor 8.2.3 external clock connections if an external clock is used, then the pins are connected as shown figure 8-4 . figure 8-4. external clock connections 8.2.4 external crystal/resonator connections if an external crystal/resonator fr equency reference is used, then th e pins are connected as shown in figure 8-5 . recommended component values are listed in the electrical characteristics chapter. figure 8-5. external frequency reference connection 8.3 register definition refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all icg registers. th is section refers to registers a nd control bits only by their names. icg xtal extal v ss clock input not connected icg extal xtal v ss c 1 c 2 crystal or resonator r f r s
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 133 8.3.1 icg control register 1 (icgc1) 76543210 r hgo 1 1 this bit can be written only once after reset. additional writes are ignored. range refs clks oscsten locd 0 w reset01000100 = unimplemented or reserved figure 8-6. icg control register 1 (icgc1) table 8-1. icgc1 register field descriptions field description 7 hgo high gain oscillator select ? the hgo bit is used to select between low power operation and high gain operation for improved noise immunity. this bit is write-once after reset. 0 oscillator configured for low power operation. 1 oscillator configured for high gain operation. 6 range frequency range select ? the range bit controls the oscillator, reference divider, and fll loop prescaler multiplication factor (p). it selects one of two refe rence frequency ranges for the icg. the range bit is write-once after a reset. the range bit only has an effect in fll engaged external and fll bypassed external modes. 0 oscillator configured for low frequency range . fll loop prescale factor p is 64. 1 oscillator configured for high frequency ra nge. fll loop prescale factor p is 1. 5 refs external reference select ? the refs bit controls the external reference clock source for icgerclk. the refs bit is write-once after a reset. 0 external clock requested. 1 oscillator using crystal or resonator requested. 4:3 clks clock mode select ? the clks bits control the clock mode as de scribed below. if fll bypassed external is requested, it will not be selected unt il ercs = 1. if the icg enters off mode, the clks bits will remain unchanged. writes to the clks bits will not take effect if a previous write is not complete. 00 self-clocked 01 fll engaged, internal reference 10 fll bypassed, external reference 11 fll engaged, external reference the clks bits are writable at any time, unless the first write after a reset was clks = 0x, the clks bits cannot be written to 1x until after the next reset (because the extal pin was not reserved). 2 oscsten enable oscillator in off mode ? the oscsten bit controls whether or not the oscillator circuit remains enabled when the icg enters off mode. this bit has no effect if hgo = 1 and range = 1. 0 oscillator disabled when icg is in off mode unless enable is high, clks = 10, and refst = 1. 1 oscillator enabled when icg is in off mode, clks = 1x and refst = 1. 1 locd loss of clock disable 0 loss of clock detection enabled. 1 loss of clock detection disabled.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 134 freescale semiconductor 8.3.2 icg control register 2 (icgc2) 76543210 r lolre mfd locre rfd w reset00000000 figure 8-7. icg control register 2 (icgc2) table 8-2. icgc2 register field descriptions field description 7 lolre loss of lock reset enable ? the lolre bit determines what type of request is made by the icg following a loss of lock indication. the lolre bit only has an effect when lols is set. 0 generate an interrupt request on loss of lock. 1 generate a reset request on loss of lock. 6:4 mfd multiplication factor ? the mfd bits control the programmable multip lication factor in the fll loop. the value specified by the mfd bits establishes the multiplication fa ctor (n) applied to the reference frequency. writes to the mfd bits will not take effect if a previous write is not complete. select a low enough value for n such that f icgdclk does not exceed its maximum specified value. 000 multiplication factor = 4 001 multiplication factor = 6 010 multiplication factor = 8 011 multiplication factor = 10 100 multiplication factor = 12 101 multiplication factor = 14 110 multiplication factor = 16 111 multiplication factor = 18 3 locre loss of clock reset enable ? the locre bit determine s how the system manages a loss of clock condition. 0 generate an interrupt request on loss of clock. 1 generate a reset request on loss of clock. 2:0 rfd reduced frequency divider ? the rfd bits control the value of the di vider following the clock select circuitry. the value specified by the rfd bits establishes the division factor (r) applied to the selected output clock source. writes to the rfd bits will not take effect if a previous write is not complete. 000 division factor = 1 001 division factor = 2 010 division factor = 4 011 division factor = 8 100 division factor = 16 101 division factor = 32 110 division factor = 64 111 division factor = 128
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 135 8.3.3 icg status register 1 (icgs1) 76543210 r clkst refst lols lock locs ercs icgif w 1 reset00000000 = unimplemented or reserved figure 8-8. icg status register 1 (icgs1) table 8-3. icgs1 register field descriptions field description 7:6 clkst clock mode status ? the clkst bits indicate the current clock mode. the clkst bits don?t update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 self-clocked 01 fll engaged, internal reference 10 fll bypassed, external reference 11 fll engaged, external reference 5 refst reference clock status ? the refst bit indicates which clock re ference is currently selected by the reference select circuit. 0 external clock selected. 1 crystal/resonator selected. 4 lols fll loss of lock status ? the lols bit is a sticky indication of fll lock status. 0 fll has not unexpectedly lost lock since lols was last cleared. 1 fll has unexpectedly lost lock since lols was last cleared, lolre determines action taken.fll has unexpectedly lost lock since lols was last cleared, lolre determines action taken. 3 lock fll lock status ? the lock bit indicates whether the fll has ac quired lock. the lock bit is cleared in off, self-clocked, and fll bypassed modes. 0 fll is currently unlocked. 1 fll is currently locked. 2 locs loss of clock status ? the locs bit is an indication of icg loss of clock status. 0 icg has not lost clock since locs was last cleared. 1 icg has lost clock since locs was last cleared, locre determines action taken. 1 ercs external reference clock status ? the ercs bit is an indication of whether or not the external reference clock (icgerclk) meets the minimum frequency requirement. 0 external reference clock is not stable, frequency requirement is not met. 1 external reference clock is stable, frequency requirement is met. 0 icgif icg interrupt flag ? the icgif read/write flag is set when an icg interrupt request is pending. it is cleared by a reset or by reading the icg status register when icgif is set and then writing a logic 1 to icgif. if another icg interrupt occurs before the clearing sequence is complete, the sequence is reset so icgif would remain set after the clear sequence was completed for the earlier interrupt. writing a logic 0 to icgif has no effect. 0 no icg interrupt request is pending. 1 an icg interrupt request is pending.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 136 freescale semiconductor 8.3.4 icg status register 2 (icgs2) 8.3.5 icg filter registers (icgfltu, icgfltl) 76543210 r0000000dcos w reset00000000 = unimplemented or reserved figure 8-9. icg status register 2 (icgs2) table 8-4. icgs2 register field descriptions field description 0 dcos dco clock stable ? the dcos bit is set when the dco clock (icg2dclk) is stable, meaning the count error has not changed by more than n unlock for two consecutive samples and the dco clock is not static. this bit is used when exiting off state if clks = x1 to determine when to switch to the requested clock mode. it is also used in self-clocked mode to determine when to start monitori ng the dco clock. this bit is cleared upon entering the off state. 0 dco clock is unstable. 1 dco clock is stable. 76543210 r0000 flt w reset00000000 = unimplemented or reserved figure 8-10. icg upper filter register (icgfltu) table 8-5. icgfltu register field descriptions field description 3:0 flt filter value ? the flt bits indicate the current filter value, which controls the dco frequency. the flt bits are read only except when the clks bits are programmed to self-clocked mode (clks = 00). in self-clocked mode, any write to icgfltu updates the current 12-bit filter value. writes to the ic gfltu register will not affect flt if a previous latch sequence is not complete.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 137 8.3.6 icg trim register (icgtrm) 8.4 functional description this section provides a functional description of eac h of the five operating modes of the icg. also discussed are the loss of clock and lo ss of lock errors and requirement s for entry into each mode. the icg is very flexible, and in some configurations, it is possible to exceed certain clock specifications. when using the fll, configure the icg so that the fre quency of icgdclk does not exceed its maximum value to ensure proper mcu operation. 76543210 r flt w reset11000000 figure 8-11. icg lower filt er register (icgfltl) table 8-6. icgfltl register field descriptions field description 7:0 flt filter value ? the flt bits indicate the current filter value, which controls the dco frequency. the flt bits are read only except when the clks bits are programmed to self-clocked mode (clks = 00). in self-clocked mode, any write to icgfltu updates the current 12-bit filter value. writes to the ic gfltu register will not affect flt if a previous latch sequence is not complete. the filter registers show the filter value (flt). 76543210 r trim w por 10000000 reset:uuuuuuuu u = unaffected by mcu reset figure 8-12. icg trim register (icgtrm) table 8-7. icgtrm register field descriptions field description 7 trim icg trim setting ? the trim bits control the internal reference generator frequency. they allow a 25% adjustment of the nominal (por) period. the bit?s effect on period is binary weighted (i.e., bit 1 will adjust twice as much as changing bit 0). increasing the binary value in trim will increase the period and decreasing the value will decrease the period.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 138 freescale semiconductor 8.4.1 off mode (off) normally when the cpu enters stop mode, the icg will cease all clock activity and is in the off state. however there are two cases to consider when cloc k activity continues while the cpu is in stop mode, 8.4.1.1 bdm active when the bdm is enabled, the icg continues activity as originally programmed. this allows access to memory and control regist ers via the bdc controller. 8.4.1.2 oscsten bit set when the oscillator is enabled in stop mode (oscsten = 1), the indivi dual clock generators are enabled but the clock feed to the rest of the mcu is turned off. this option is provided to avoid long oscillator startup times if necessary, or to run the rti from the oscillator during stop3. 8.4.1.3 stop/off mode recovery upon the cpu exiting stop mode due to an interrupt, the previously set control bits are valid and the system clock feed resumes. if fee is select ed, the icg will source the internal reference until th e external clock is stable. if fbe is selected, the icg will wait for the external clock to stabilize before enabling icgout. upon the cpu exiting stop mode due to a reset, the previously set icg control bits are ignored and the default reset values applied. therefore the icg will exit stop in scm mode configured for an approximately 8 mhz dco output (4 mhz bus clock) with trim value maintained. if using a crystal, 4096 clocks are detected prior to engaging icgerclk. this is incorporated in crystal start-up time. 8.4.2 self-clocked mode (scm) self-clocked mode (scm) is the de fault mode of operation and is en tered when any of the following conditions occur: ? after any reset. ? exiting from off mode when clks does not e qual 10. if clks = x1, the icg enters this state temporarily until the dco is stable (dcos = 1). ? clks bits are written from x1 to 00. ? clks = 1x and icgerclk is not detected (both ercs = 0 and locs = 1). in this state, the fll loop is open. the dco is on, a nd the output clock signal ic gout frequency is given by f icgdclk / r. the icgdclk frequency can be varied from 8 mhz to 40 mhz by writing a new value into the filter registers (icgflth and icgfltl). this is the only mode in which the filter registers can be written. if this mode is ente red due to a reset, f icgdclk will default to f self_reset which is nominally 8 mhz. if this mode is entered from fll engaged internal, f icgdclk will maintain the previous frequency.if this mode is entered from fll engaged external (either by progr amming clks or due to a loss of external reference clock), f icgdclk will maintain the previous fr equency, but icgout will doubl e if the fll was unlocked. if this mode is entered from off mode, f icgdclk will be equal to the frequency of icgdclk before
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 139 entering off mode. if clks bits are set to 01 or 11 co ming out of the off state, the icg enters this mode until icgdclk is stable as determ ined by the dcos bit. after icgdclk is considered stable, the icg automatically closes the loop by switching to fll enga ged (internal or external) as selected by the clks bits. figure 8-13. detailed frequency-locked loop block diagram 8.4.3 fll engaged, internal clock (fei) mode fll engaged internal (fei) is entered wh en any of the following conditions occur: ? clks bits are written to 01 ? the dco clock stabilizes (dcos = 1) while in scm upon exiting the off state with clks = 01 in fll engaged internal mode, th e reference clock is derived from the internal reference clock icgirclk, and the fll loop will attempt to lock the icgdclk frequency to the desired value, as selected by the mfd bits. reference divider (/7) subtractor loop filter digitally controlled oscillator clock icgout icg2dclk reset and interrupt irq fll analog select circuit pulse counter frequency- icgerclk lock and detector control reset reduced frequency divider (r) loss of clock icgdclk loop (fll) digital counter enable locked overflow 1x 2x icgirclk clkst range mfd range clks rfd flt locre clkst lolre icgif locd ercs locs lols lock dcos
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 140 freescale semiconductor 8.4.4 fll engaged internal unlocked fei unlocked is a temporary state that is ente red when fei is entere d and the count error ( n) output from the subtractor is greater than the maximum n unlock or less than the minimum n unlock , as required by the lock detector to detect the unlock condition. the icg will remain in this state while the count error ( n) is greater than the maximum n lock or less than the minimum n lock , as required by the lock detect or to detect the lock condition. in this state the output clock signa l icgout frequency is given by f icgdclk / r. 8.4.5 fll engaged internal locked fll engaged internal locked is entered from fei unloc ked when the count error ( n), which comes from the subtractor, is less than n lock (max) and greater than n lock (min) for a given number of samples, as required by the lock detector to de tect the lock condition. the output clock signal icgout frequency is given by f icgdclk / r. in fei locked, the filter value is updated only once every four comparison cycles. the update made is an average of the error measurements taken in the four previous comparisons. 8.4.6 fll bypassed, external clock (fbe) mode fll bypassed external (fbe) is entered when any of the following conditions occur: ? from scm when clks = 10 and ercs is high ? when clks = 10, ercs = 1 upon entering off mode, and off is then exited ? from fll engaged external mode if a loss of dco clock occurs and the exte rnal reference remains valid (both locs = 1 and ercs = 1) in this state, the dco and irg are off and the referenc e clock is derived from th e external reference clock, icgerclk. the output clock signal icgout frequency is given by f icgerclk / r. if an external clock source is used (refs = 0), then the input frequenc y on the extal pin can be anywhere in the range 0 mhz to 40 mhz. if a crystal or resonator is used (refs = 1), then frequency range is either low for range = 0 or high for range = 1. 8.4.7 fll engaged, external clock (fee) mode the fll engaged external (fee) mode is entere d when any of the following conditions occur: ? clks = 11 and ercs and dcos are both high. ? the dco stabilizes (dcos = 1) while in scm upon exiting the off state with clks = 11. in fee mode, the reference clock is derived from the external refe rence clock icgerclk, and the fll loop will attempt to lock the icgdclk frequency to th e desired value, as selected by the mfd bits. to run in fee mode, there must be a working 32 khz ?100 khz or 2 mhz?10 mhz external clock source. the maximum external clock frequency is limited to 10 mhz in fee mode to prevent over-clocking the dco. the minimum multiplier for the fll, from table 8-12 is 4. because 4 x 10 mhz is 40mhz, which is the operational limit of the dco, the reference clock cannot be any faster than 10 mhz.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 141 8.4.7.1 fll engaged external unlocked fee unlocked is entered when fee is entered and the count error ( n) output from the s ubtractor is greater than the maximum n unlock or less than the minimum n unlock , as required by the lock detector to detect the unlock condition. the icg will remain in this state while the count error ( n) is greater than the maximum n lock or less than the minimum n lock , as required by the lock detect or to detect the lock condition. in this state, the pulse counter, s ubtractor, digital loop filt er, and dco form a closed loop and attempt to lock it according to their operational descriptions later in this secti on. upon entering this state and until the fll becomes locked, the output clock signal icgout frequency is given by f icgdclk / (2 r) this extra divide by two prevents frequency overshoots dur ing the initial locking process from exceeding chip-level maximum frequenc y specifications. after the fll has lock ed, if an unexpected loss of lock causes it to re-enter the unlocke d state while the icg remains in fee mode, the output clock signal icgout frequency is given by f icgdclk / r. 8.4.7.2 fll engaged external locked fee locked is entered from fee unlocked when the count error ( n) is less than n lock (max) and greater than n lock (min) for a given number of samples, as requi red by the lock detector to detect the lock condition. the output clock signal ic gout frequency is given by f icgdclk /r. in fll engaged external locked, the filter value is updated only once every four comparison cycles. the update made is an average of the error measurements taken in the four previous comparisons. 8.4.8 fll lock and loss-of-lock detection to determine the fll locked and loss-of-lock condi tions, the pulse counter c ounts the pulses of the dco for one comparison cycle (see table 8-9 for explanation of a comparison cycle) and passes this number to the subtractor. the subtr actor compares this value to the valu e in mfd and produces a count error, n. to achieve locked status, n must be between n lock (min) and n lock (max). after the fll has locked, n must stay between n unlock (min) and n unlock (max) to remain locked. if n goes outside this range unexpectedly, the lols status bit is set and remains set until clear ed by software or until the mcu is reset. lols is cleared by reading icgs1 then writ ing 1 to icgif (lolre = 0), or by a loss-of-lock induced reset (lolre = 1), or by any mcu reset. if the icg enters the off state due to stop mode when enbdm = oscsten = 0, the fll loses locked status (lock is cleared), but lols remains unchanged because this is not an unexpected loss-of-lock condition. though it would be unusual, if enbdm is cleared to 0 while th e mcu is in stop, the icg enters the off state. because this is an unexpected stopping of clocks, lols will be set when the mcu wakes up from stop. expected loss of lock occurs when the mfd or clks bits are changed or in fei mode only, when the trim bits are changed. in these cases, the lock bit will be cleared until the fll regains lock, but the lols will not be set.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 142 freescale semiconductor 8.4.9 fll loss-of-clock detection the reference clock and the dco clock are monitored under different conditions (see table 8-8 ). provided the reference frequency is being monitored, ercs = 1 indicates that the reference clock meets minimum frequency requirements. when the re ference and/or dc o clock(s) are being monito red, if either one falls below a certain frequency, f lor and f lod , respectively, the locs status bit wi ll be set to indicate the error. locs will remain set until it is acknowledged or unt il the mcu is reset. locs is cleared by reading icgs1 then writing 1 to icgif (lo cre = 0), or by a loss-of-clock indu ced reset (locre = 1), or by any mcu reset. if the icg is in fee, a loss of reference clock causes the icg to enter scm, and a loss of dco clock causes the icg to enter fbe mode. if the icg is in fbe m ode, a loss of reference clock will cause the icg to enter scm. in each case, the clkst and clks bits will be automatically changed to reflect the new state. if the icg is in fee mode when a lo ss of clock occurs and the ercs is still set to 1, then the clkst bits are set to 10 and the icg reverts to fbe mode. a loss of clock will also cause a loss of lock when in fee or fei modes. b ecause the method of clearing the locs and lols bits is the same, this would onl y be an issue in the unlikely case that lolre = 1 and locre = 0. in this case, the interrupt would be overridden by the reset for the loss of lock. table 8-8. clock monitoring (when locd = 0) mode clks refst ercs external reference clock monitored? dco clock monitored? off 0x or 11 x forced low no no 10 0 forced low no no 10 1 real-time 1 1 if enable is high (waiting for external crystal start-up after exiting stop). ye s (1) no scm (clkst = 00) 0x x forced low no yes 2 2 dco clock will not be monitored until dcos = 1 upon enteri ng scm from off or fll bypassed external mode. 10 0 forced high no yes (2) 10 1 real-time yes yes (2) 11 x real-time yes yes (2) fei (clkst = 01) 0x x forced low no yes 11 x real-time yes yes fbe (clkst = 10) 10 0 forced high no no 10 1 real-time yes no fee (clkst = 11) 11 x real-time yes yes
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 143 8.4.10 clock mode requirements a clock mode is requested by writ ing to clks1:clks0 and the actu al clock mode is indicated by clkst1:clkst0. provided minimum c onditions are met, the status shown in clkst1:clkst0 should be the same as the reques ted mode in clks1:clks0. table 8-9 shows the relationship between clks, clkst, and icgout. it also shows the condi tions for clks = clkst or the reason clks clkst. note if a crystal will be used before the next reset, then be sure to set refs = 1 and clks = 1x on the first write to the ic gc1 register. failure to do so will result in ?locking? refs = 0 which wi ll prevent the oscillator amplifier from being enabled until the next reset occurs. table 8-9. icg state table actual mode (clkst) desired mode (clks) range reference frequency (f reference ) comparison cycle time icgout conditions 1 for clks = clkst 1 clkst will not update immediately after a write to clks. seve ral bus cycles are required before clkst updates to the new value. reason clks1 clkst off (xx) off (xx) x0 ? 0 ? ? fbe (10) x 0 ? 0 ? ercs = 0 scm (00) scm (00) x f icgirclk /7 2 2 the reference frequency has no effect on icgout in scm, but the reference frequency is still used in making the comparisons that determine the dcos bit 8/f icgirclk icgdclk/r not switching from fbe to scm ? fei (01) 0 f icgirclk /7 (1) 8/f icgirclk icgdclk/r ? dcos = 0 fbe (10) x f icgirclk /7 (1) 8/f icgirclk icgdclk/r ? ercs = 0 fee (11) x f icgirclk /7 (1) 8/f icgirclk icgdclk/r ? dcos = 0 or ercs = 0 fei (01) fei (01) 0 f icgirclk /7 8/f icgirclk icgdclk/r dcos = 1 ? fee (11) x f icgirclk /7 8/f icgirclk icgdclk/r ? ercs = 0 fbe (10) fbe (10) x 0 ? icgerclk/r ercs = 1 ? fee (11) x 0 ? icgerclk/r ? locs = 1 & ercs = 1 fee (11) fee (11) 0 f icgerclk 2/f icgerclk icgdclk/r 3 3 after initial lock; will be icgdclk/2r duri ng initial locking process and while fll is re-locking after the mfd bits are change d. ercs = 1 and dcos = 1 ? 1 f icgerclk 128/f icgerclk icgdclk/r (2) ercs = 1 and dcos = 1 ?
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 144 freescale semiconductor 8.4.11 fixed frequency clock the icg provides a fixed frequency clock output, xclk, for use by on-chip peripherals. this output is equal to the internal bus clock, busclk, in all modes except fee. in fee mode, xclk is equal to icgerclk 2 when the following conditions are met: ?(p n) r 4 where p is determined by range (see table 8-11 ), n and r are determined by mfd and rfd respectively (see table 8-12 ). ? lock = 1. if the above conditions are not true, then xclk is equal to busclk. when the icg is in either fei or scm mode, xclk is turned off. any peripherals which can use xclk as a clock source must not do so when the icg is in fei or scm mode. 8.4.12 high gain oscillator the oscillator has the option of running in a hi gh gain oscillator (hgo) mode, which improves the oscillator's resistance to emc noise when running in fbe or fee modes. this option is se lected by writing a 1 to the hgo bit in the icgc1 regi ster. hgo is used with both the hi gh and low range os cillators but is only valid when refs = 1 in the icgc1 register. wh en hgo = 0, the standard low-power oscillator is selected. this bit is writab le only once after any reset. 8.5 initialization/application information 8.5.1 introduction the section is intended to give some basic direction on which configurat ion a user would want to select when initializing the icg. for some applications, th e serial communication link may dictate the accuracy of the clock reference. for othe r applications, lowest power cons umption may be the chief clock consideration. still others may have lowest cost as the primary goal. th e icg allows great flexibility in choosing which is best for any application.
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 145 the following sections cont ain initialization examples for various configurations. note hexadecimal values designated by a pr eceding $, binary values designated by a preceding %, and decimal valu es have no preceding character. important configuration information is repeated here for reference. table 8-10. icg configuration consideration clock reference source = internal clock reference source = external fll engaged fei 4 mhz < f bus < 20 mhz. medium power (will be less than fee if oscillator range = high) good clock accuracy (after irg is trimmed) lowest system cost (no external components required) irg is on. dco is on. 1 1 the irg typically consumes 100 a. the fll and dco typically consumes 0.5 to 2.5 ma, depending upon output frequency. for minimum power consumption and minimum jitter, choose n and r to be as small as possible. fee 4 mhz < f bus < 20 mhz medium power (will be less than fei if oscillator range = low) high clock accuracy medium/high system cost (crystal, resonator or external clock source required) irg is off. dco is on. fll bypassed scm this mode is mainly provided for quick and reliable system startup. 3 mhz < f bus < 5 mhz (default). 3 mhz < f bus < 20 mhz (via filter bits). medium power poor accuracy. irg is off. dco is on and open loop. fbe f bus range 8 mhz when crystal or resonator is used. lowest power highest clock accuracy medium/high system cost (crystal, resonator or external clock source required) irg is off. dco is off. table 8-11. icgout frequency calculation options clock scheme f icgout 1 1 ensure that f icgdclk , which is equal to f icgout * r, does not exceed f icgdclkmax . pnote scm ? self-clocked mode (fll bypassed internal) f icgdclk / r na typical f icgout = 8 mhz immediately after reset fbe ? fll bypassed external f ext / r na fei ? fll engaged internal (f irg / 7)* 64 * n / r 64 typical f irg = 243 khz fee ? fll engaged external f ext * p * n / r range = 0 ; p = 64 range = 1; p = 1 table 8-12. mfd and rfd decode table mfd value multiplication factor (n) rfd division factor (r) 000 4 000 1 001 6 001 2 010 8 010 4 011 10 011 8 100 12 100 16
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 146 freescale semiconductor 8.5.2 example #1: external crystal = 32 khz, bus frequency = 4.19 mhz in this example, the fll will be used (in fee mode ) to multiply the external 32 khz oscillator up to 8.38 mhz to achieve 4.19 mhz bus frequency. after the mcu is released from reset, the icg is in self-clocked mode (scm) and s upplies approximately 8 mhz on icgout, which corresponds to a 4 mhz bus frequency (f bus ). the clock scheme will be f ll engaged, external (fee). so f icgout = f ext * p * n / r ; p = 64, f ext = 32 khz eqn. 8-1 solving for n / r gives: n / r = 8.38 mhz /(32 khz * 64) = 4 ; we can choose n = 4 and r =1 eqn. 8-2 the values needed in each register to set up the desired operation are: icgc1 = $38 (%00111000) bit 7 hgo 0 configures oscillator for low power bit 6 range 0 configures oscillator for low-fr equency range; fll prescale factor is 64 bit 5 refs 1 oscillator using crys tal or resonator is requested bits 4:3 clks 11 fll engaged, ex ternal reference clock mode bit 2 oscsten 0 oscillator disabled bit 1 locd 0 loss-of-clock detection enabled bit 0 0 unimplemented or re served, always reads zero icgc2 = $00 (%00000000) bit 7 lolre 0 generates an interrupt request on loss of lock bits 6:4 mfd 000 sets the mfd multiplication factor to 4 bit 3 locre 0 generates an interrupt request on loss of clock bits 2:0 rfd 000 sets the rfd division factor to 1 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only; should read dcos = 1 before performing any time critical tasks icgfltlu/l = $xx only needed in self-clocked mode; flt will be adjusted by loop to give 8.38 mhz dco clock bits 15:12 unused 0000 101 14 101 32 110 16 110 64 111 18 111 128 table 8-12. mfd and rfd decode table
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 147 bits 11:0 flt no need for user initialization icgtrm = $xx bits 7:0 trim only need to write when trimming internal oscillator; not used when external crystal is clock source figure 8-14 shows flow charts for three c onditions requiring icg initialization. figure 8-14. icg initialization for fee in example #1 reset continue recovery from stop check lock = 1? no yes fll lock status. initialize icg icgc1 = $38 icgc2 = $00 recovery from stop oscsten = 1 oscsten = 0 continue check lock = 1? no yes fll lock status. continue check lock = 1? no yes fll lock status. note: this will require the oscillator to start and stabilize. actual time is dependent on crystal /resonator and external circuitry. quick recovery from stop minimum current draw in stop
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 148 freescale semiconductor 8.5.3 example #2: external crystal = 4 mhz, bus frequency = 20 mhz in this example, the fll will be used (in fee mode ) to multiply the external 4 mhz oscillator up to 40-mhz to achieve 20 mhz bus frequency. after the mcu is released from reset, the icg is in self-clocked mode (scm) and s upplies approximately 8 mhz on icgout which corresponds to a 4 mhz bus frequency (f bus ). during reset initialization software, the clock scheme will be set to fll engaged, external (fee). so f icgout = f ext * p * n / r ; p = 1, f ext = 4.00 mhz eqn. 8-3 solving for n / r gives: n / r = 40 mhz /(4 mhz * 1) = 10 ; we can choose n = 10 and r = 1 eqn. 8-4 the values needed in each register to set up the desired operation are: icgc1 = $78 (%01111000) bit 7 hgo 0 configures oscillator for low power bit 6 range 1 configures oscillator for high- frequency range; fll pr escale factor is 1 bit 5 refs 1 requests an oscillator bits 4:3 clks 11 fll engaged, ex ternal reference clock mode bit 2 oscsten 0 disables the oscillator bit 1 locd 0 loss-of-clock detection enabled bit 0 0 unimplemented or re served, always reads zero icgc2 = $30 (%00110000) bit 7 lolre 0 generates an interrupt request on loss of lock bit 6:4 mfd 011 sets the mfd multiplication factor to 10 bit 3 locre 0 generates an interrupt request on loss of clock bit 2:0 rfd 000 sets the rfd division factor to 1 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only. should read dcos befo re performing any time critical tasks icgfltlu/l = $xx not used in this example icgtrm not used in this example
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 149 figure 8-15. icg initialization and stop recovery for example #2 reset continue recovery check lock = 1? no yes fll lock status initialize icg icgc1 = $7a icgc2 = $30 continue check lock = 1? no yes fll lock status service interrupt source (f bus = 4 mhz) from stop
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 150 freescale semiconductor 8.5.4 example #3: no external cr ystal connection, 5.4 mhz bus frequency in this example, the fll will be used (in fei mode) to multiply the internal 243 khz (approximate) reference clock up to 10.8 mhz to ac hieve 5.4 mhz bus frequency. this system will also use the trim function to fine tune the frequency based on an external reference signal. after the mcu is released from reset, the icg is in self-clocked mode (scm) and s upplies approximately 8 mhz on icgout which corresponds to a 4 mhz bus frequency (f bus ). the clock scheme will be fll engaged, internal (fei). so f icgout = (f irg / 7) * p * n / r ; p = 64, f irg = 243 khz eqn. 8-5 solving for n / r gives: n / r = 10.8 mhz /(243/7 khz * 64) = 4.86 ; we can choose n = 10 and r = 2. eqn. 8-6 a trim procedure will be required to hone the frequency to exac tly 5.4 mhz. an example of the trim procedure is shown in example #4. the values needed in each register to set up the desired operation are: icgc1 = $28 (%00101000) bit 7 hgo 0 configures oscillator for low power bit 6 range 0 configures oscillator for low-fr equency range; fll prescale factor is 64 bit 5 refs 1 oscillator using crystal or resona tor requested (bit is really a don?t care) bits 4:3 clks 01 fll engaged, in ternal reference clock mode bit 2 oscsten 0 disables the oscillator bit 1 locd 0 loss-of-clock enabled bit 0 0 unimplemented or re served, always reads zero icgc2 = $31 (%00110001) bit 7 lolre 0 generates an interrupt request on loss of lock bit 6:4 mfd 011 sets the mfd multiplication factor to 10 bit 3 locre 0 generates an interrupt request on loss of clock bit 2:0 rfd 001 sets the rfd division factor to 2 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only; good idea to read this before performing time critical operations icgfltlu/l = $xx not used in this example
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 151 icgtrm = $xx bit 7:0 trim only need to write when trimmin g internal oscillator ; done in separate operation (see example #4) figure 8-16. icg initialization and stop recovery for example #3 reset continue check lock = 1? no yes fll lock status. initialize icg icgc1 = $28 icgc2 = $31 recovery continue check lock = 1? no yes fll lock status. note: this will require the interal reference clock to start and stabilize. from stop
internal clock generator (s08icgv4) mc9s08ac16 series data sheet, rev. 8 152 freescale semiconductor 8.5.5 example #4: internal clock generator trim the internally generated clock sour ce is guaranteed to have a period 25% of the nominal value. in some cases, this may be sufficient accuracy. for other appl ications that require a ti ght frequency tolerance, a trimming procedure is provided that will allow a very accurate source. this section outlines one example of trimming the internal oscillator. many other possi ble trimming procedures are valid and can be used. figure 8-17. trim procedure in this particular case, the mcu ha s been attached to a pcb and the entire assembly is undergoing final test with automated test equipment. a separate si gnal or message is provided to the mcu operating under user provided software contro l. the mcu initiates a trim procedure as outlined in figure 8-17 while the tester supplies a precision reference signal. if the intended bus frequency is near the maximum allowed fo r the device, it is re commended to trim using a reduction divisor (r) twice the final value. after th e trim procedure is comp lete, the reduction divisor can be restored. this will prevent accident al overshoot of the maximum clock frequency. initial conditions: 1) clock supplied from ate has 500 sec duty period 2) icg configured for inter nal reference with 4 mhz bus start trim procedure continue case statement count > expected = 500 . measure incoming clock width icgtrm = $80, n = 1 count < expected = 500 count = expected = 500 store icgtrm value in non-volatile memory icgtrm = icgtrm = icgtrm - 128 / (2**n) icgtrm + 128 / (2**n) n = n + 1 (count = # of bus clocks / 4) (decreasing icgtrm increases the frequency) (increasing icgtrm decreases the frequency) no yes is n > 8? (running too slow) (running too fast)
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 153 chapter 9 keyboard interrupt (s08kbiv1) 9.1 introduction the mc9s08ac16 series has one kbi module with seven keyboard inte rrupt inputs that are shared with port d and port g pins. see chapter 2, ?pins and connections ,? for more information about the logic and hardware aspects of these pins. note bit 7 of kbisc and kbipe is reserved and reads 0. neglect the correlative information in section 9.4.1, ?kbi status and control register (kbisc) ,? and section 9.4.2, ?kbi pin enab le register (kbipe) .? 9.2 keyboard pin sharing the kbi input kbip6 shares a comm on pin with ptd3 and ad11, and kbi input kbip5 shares a common pin with ptd2 and ad10. the kbi inputs kbip4?kbip0 are shar ed on common pins with ptg4?ptg0. kbip3?kbip0 are always falling- edge/low-level sensitive. kbip6?k bip4 can be configured for rising-edge/high-level or for falli ng-edge/low-level sensitivity. when any of the inputs kbip6?kbip0 are enabled and configured to detect rising edges/hi gh levels, and the pin pullup is enabled through the corresponding port pullup enable bit for that pin, a pulldown resistor rather than a pullup resistor is enabled on the pin. 9.3 features the keyboard interrupt (kbi ) module features include: ? four falling edge/low level sensitive ? three falling edge/low level or rising edge/high level sensitive ? choice of edge-only or edge-and-level sensitivity ? common interrupt flag and interrupt enable control ? capable of waking up the mcu from stop3, stop2, or wait mode
chapter 9 keyboard interrupt (s08kbiv1) mc9s08ac16 series data sheet, rev. 8 154 freescale semiconductor figure 9-1. mc9s08ac16 block diagram highlighting the kbi ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pulld own devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
keyboard interrupt (s08kbiv1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 155 9.3.1 kbi block diagram figure 9-2 shows the block diagram for a kbi module. figure 9-2. kbi block diagram 9.4 register definition this section provides information about all register s and control bits associated with the kbi module. refer to the direct-page register summ ary in the memory chapter of this data sheet for the absolute address assignments for all kbi registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. keyboard interrupt dq ck clr v dd kbimod kbie keyboard interrupt ff request kback reset synchronizer kbf stop bypass stop busclk kbipen 0 1 s kbedgn kbipe0 kbipe3 kbipe4 0 1 s kbedg4 kbip0 kbip3 kbip4 kbipn
keyboard interrupt (s08kbiv1) mc9s08ac16 series data sheet, rev. 8 156 freescale semiconductor 9.4.1 kbi status and control register (kbisc) 76543210 r kbedg7 kbedg6 kbedg5 kbedg4 kbf 0 kbie kbimod w kback reset00000000 = unimplemented or reserved figure 9-3. kbi status and control register (kbisc) table 9-1. kbisc register field descriptions field description 7:4 kbedg[7:4] keyboard edge select for kbi port bits ? each of these read/write bits sele cts the polarity of the edges and/or levels that are recognized as trigger events on the corresp onding kbi port pin when it is configured as a keyboard interrupt input (kbipen = 1). also see the kbimod control bit, which determines whether the pin is sensitive to edges-only or edges and levels. 0 falling edges/low levels 1 rising edges/high levels 3 kbf keyboard interrupt flag ? this read-only status flag is set whenever the selected edge event has been detected on any of the enabled kbi port pins. this flag is cleared by writing a 1 to the kback control bit. the flag will remain set if kbimod = 1 to select edge-and-level operation and any enabled kbi port pin remains at the asserted level. kbf can be used as a software pollable flag (kbie = 0) or it can generate a hardware interrupt request to the cpu (kbie = 1). 0 no kbi interrupt pending 1 kbi interrupt pending 2 kback keyboard interrupt acknowledge ? this write-only bit (reads always return 0) is used to clear the kbf status flag by writing a 1 to kback. when kbimod = 1 to sele ct edge-and-level operation and any enabled kbi port pin remains at the asserted level, kbf is being continuous ly set so writing 1 to kback does not clear the kbf flag. 1 kbie keyboard interrupt enable ? this read/write control bit determines whether hardware interrupts are generated when the kbf status flag equals 1. when kbie = 0, no hardware interrupt s are generated, but kbf can still be used for software polling. 0 kbf does not generate hardware interrupts (use polling) 1 kbi hardware interrupt requested when kbf = 1 kbimod keyboard detection mode ? this read/write control bit selects either edge-only detection or edge-and-level detection. kbi port bits 3 through 0 can detect falling edges-only or falling edges and low levels. kbi port bits 7 through 4 can be configured to detect either: ? rising edges-only or rising edges and high levels (kbedgn = 1) ? falling edges-only or falling edges and low levels (kbedgn = 0) 0 edge-only detection 1 edge-and-level detection
keyboard interrupt (s08kbiv1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 157 9.4.2 kbi pin enable register (kbipe) 9.5 functional description 9.5.1 pin enables the kbipen control bits in the kbipe register allo w a user to enable (kbipen = 1) any combination of kbi-related port pins to be conn ected to the kbi module. pins co rresponding to 0s in kbipe are general-purpose i/o pins that are not associated with the kbi module. 9.5.2 edge and level sensitivity synchronous logic is used to detect edges. prior to detecting an edge, enabled keyboard inputs in a kbi module must be at the deasserted logic level. a falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the i nput signal is seen as a logic 0 during one bus cy cle and then a logic 1 during the next cycle. the kbimod control bit can be set to reconfigure the de tection logic so that it detects edges and levels. in kbimod = 1 mode, the kbf status flag becomes set when an edge is detected (when one or more enabled pins change from the deassert ed to the asserted level while all other enabled pins remain at their deasserted levels), but th e flag is continuously set (and cannot be cleared) as long as any enabled keyboard input pin remains at the asserted level. when the mcu enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). in stop mode, kbi inputs act as asynchronous level-sensitive inputs so they can wake the mcu from stop mode. 76543210 r kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 w reset00000000 = unimplemented or reserved figure 9-4. kbi pin enable register (kbipe) table 9-2. kbipe register field descriptions field description 7:0 kbipe[7:0] keyboard pin enable for kbi port bits ? each of these read/write bits selects whether the associated kbi port pin is enabled as a keyboard interrupt input or functions as a general-purpose i/o pin. 0 bit n of kbi port is a general-purpose i/o pin not associated with the kbi 1 bit n of kbi port enabled as a keyboard interrupt input
keyboard interrupt (s08kbiv1) mc9s08ac16 series data sheet, rev. 8 158 freescale semiconductor 9.5.3 kbi interrupt controls the kbf status flag becomes set (1) when an edge event has been detected on any kbi input pin. if kbie = 1 in the kbisc register, a hardware interrupt will be request ed whenever kbf = 1. the kbf flag is cleared by writing a 1 to th e keyboard acknowledge (kback) bit. when kbimod = 0 (selecting edge- only operation), kbf is always cleared by writing 1 to kback. when kbimod = 1 (selecting edge-a nd-level operation), kbf cannot be cleared as long as any keyboard input is at its asserted level.
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 159 chapter 10 timer/pwm (s08tpmv3) 10.1 introduction the mc9s08ac16 series includes three indepe ndent timer/pwm (tpm) modules which support traditional input capture, output compare, or buf fered edge-aligned pulse-wid th modulation (pwm) on each channel. a control bit in each tpm configures all channels in that timer to operate as center-aligned pwm functions. in each tpm, timing functions are based on a separa te 16-bit counter with prescaler and modulo features to control frequency and range (peri od between overflows) of th e time reference. this timing system is ideally suited fo r a wide range of control appli cations, and the center-aligned pwm capability on the tpm extends the field of applic ations to motor control in small appliances. the use of the fixed system clock, xclk, as the clock sour ce for any of the tpm modules allows the tpm prescaler to run using the oscillat or rate divided by two (icgerclk/2) . this option is only available if the icg is configured in fee mode and the proper conditions are met (see section 8.4.11, ?fixed frequency clock ?). in all other icg modes th is selection is re dundant because xclk is the same as busclk. an external clock source can be connected to th e tpmclk pin. the maximum frequency for tpmclk is the bus clock frequency divided by 4. all three tpm modules can inde pendently select tpmclk as the clock source. 10.2 features the timer system in the mc9s08ac 16 series includes a 4-channel tpm 1, a separate 2-channel tpm2 and a separate 2-channel tpm3. ti mer system features include: ? a total of up to eight channels: ? each channel may be input capture, output compare, or buffered edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs ? each tpm may be configured fo r buffered, center-aligned pulse-w idth modulation (cpwm) on all channels ? clock source to prescaler for each tpm is inde pendently selectable as bus clock, fixed system clock, or an external pin: ? prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 ? external clock input: tpmclk for use by tpm1, tpm2, and/or tpm3 ? 16-bit free-running or up/ down (cpwm) count operation ? 16-bit modulus register to control counter range ? timer system enable ? one interrupt per channel plus a termin al count interrupt for each tpm module
chapter 10 timer/pwm (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 160 freescale semiconductor figure 10-1. mc9s08ac16 block diagram highlighting the tpm ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
chapter 10 timer/pwm (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 161 10.3 tpmv3 differences from previous versions the tpmv3 is the latest version of the timer/pw m module that addresses e rrata found in previous versions. the following section outlines the differences between tpmv3 and tpmv2 modules, and any considerations that should be taken when porting code. table 10-1. tpmv2 and tpmv3 porting considerations action tpmv3 tpmv2 write to tpmxcnth:l registers 1 any write to tpmxcnth or tpmxcntl registers clears the tpm counter (tpmxcnth:l) and the prescaler counter. clears the tpm counter (tpmxcnth:l) only. read of tpmxcnth:l registers 1 in bdm mode, any read of tpmxcnth:l r egisters returns the value of the tpm counter that is frozen. if only one byte of the tpmxcnth:l registers was read before the bdm mode became active, returns the latched value of tpmxcnth:l from the read buffer (instead of the frozen tpm counter value). in bdm mode, a write to tpmxsc, tpmxcnth or tpmxcntl clears this read coherency mechanism. does not clear this read coherency mechanism. read of tpmxcnvh:l registers 2 in bdm mode, any read of tpmxcnvh:l registers returns the value of the tpmxcnvh:l register. if only one byte of the tpmxcnvh:l registers was read before the bdm mode became active, returns the latched value of tpmxcnth:l from the read buffer (instead of the value in the tpmxcnvh:l registers). in bdm mode, a write to tpmxcnsc clears this read coherency mechanism. does not clear this read coherency mechanism. write to tpmxcnvh:l registers in input capture mode, writes to tpmxcnvh:l registers 3 not allowed. allowed. in output compare mode, when (clksb:clksa not = 0:0), writes to tpmxcnvh:l registers 3 update the tpmxcnvh:l registers with the value of their write buffer at the next change of the tpm counter (end of the prescaler counting) after the second byte is written. always update these registers when their second byte is written.
chapter 10 timer/pwm (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 162 freescale semiconductor in edge-aligned pwm mode when (clksb:clksa not = 00), writes to tpmxcnvh:l registers update the tpmxcnvh:l registers with the value of their write buffer after both bytes were written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). note: if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. update after both bytes are written and when the tpm counter changes from tpmxmodh:l to $0000. in center-aligned pwm mode when (clksb:clksa not = 00), writes to tpmxcnvh:l registers 4 update the tpmxcnvh:l registers with the value of their write buffer after both bytes are written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). note: if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. update after both bytes are written and when the tpm counter changes from tpmxmodh:l to (tpmxmodh:l - 1). center-aligned pwm when tpmxcnvh:l = tpmxmodh:l 5 produces 100% duty cycle. produces 0% duty cycle. when tpmxcnvh:l = (tpmxmodh:l - 1) 6 produces a near 100% duty cycle. produces 0% duty cycle. tpmxcnvh:l is changed from 0x0000 to a non-zero value 7 waits for the start of a new pwm period to begin using the new duty cycle setting. changes the channel output at the middle of the current pwm period (when the count reaches 0x0000). tpmxcnvh:l is changed from a non-zero value to 0x0000 8 finishes the current pwm period using the old duty cycle setting. finishes the current pwm period using the new duty cycle setting. write to tpmxmodh:l registers in bdm mode in bdm mode, a write to tpmxsc register clears the write coherency mechanism of tpmxmodh:l registers. does not clear the write coherency mechanism. 1 for more information, refer to section 10.5.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) .? [se110-tpm case 7] 2 for more information, refer to section 10.5.5, ?tpm channel valu e registers (tpmxcnvh:tpmxcnvl) .? 3 for more information, refer to section 10.6.2.1, ?input capture mode .? 4 for more information, refer to section 10.6.2.4, ?center-aligned pwm mode .? 5 for more information, refer to section 10.6.2.4, ?center-aligned pwm mode .? [se110-tpm case 1] 6 for more information, refer to section 10.6.2.4, ?center-aligned pwm mode .? [se110-tpm case 2] 7 for more information, refer to section 10.6.2.4, ?center-aligned pwm mode .? [se110-tpm case 3 and 5] table 10-1. tpmv2 and tpmv3 porting considerations (continued) action tpmv3 tpmv2
chapter 10 timer/pwm (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 163 10.3.1 migrating from tpmv1 in addition to section 10.3, ?tpmv3 differen ces from previous versions ,? keep in mind the following considerations when migrating from a device that uses tpmv1. ? you can write to the channel value register (tpm xcnv) when the timer is not in input capture mode for tpmv2, not tpmv3. ? in edge- or center- aligned modes, the channe l value register (tpmxc nv) registers only update when the timer changes from tpmmod-1 to tp mmod, or in the case of a free running timer from 0xfffe to 0xffff. ? also, when configuring the tpm modules, it is be st to write to tpmxsc before tpmxcnv as a write to tpmxsc resets the coherenc y mechanism on the tpmxcnv registers. 8 for more information, refer to section 10.6.2.4, ?center-aligned pwm mode .? [se110-tpm case 4] table 10-2. migrating to tpmv3 considerations when... action / best practice writing to the channel value register (tpmxcnv) register... timer must be in input capture mode. updating the channel value register (tpmxcnv) register in edge-aligned or center-aligned modes... only occurs when the timer changes from tpmmod-1 to tpmmod (or in the case of a free running timer, from 0xfffe to 0xffff). reseting the coherency mechanism for the channel value register (tpmxcnv) register... write to tpmxsc. configuring the tpm modules... write first to tpmxsc and then to tpmxcnv register.
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 164 freescale semiconductor 10.3.2 features the tpm includes these distinctive features: ? one to eight channels: ? each channel may be input capture, output compare, or edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs ? module may be configured for buffered, center-aligned pulse-w idth-modulation (cpwm) on all channels ? timer clock source selectable as prescaled bus cl ock, fixed system clock, or an external clock pin ? prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 ? fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit ? external clock pin may be shared with any timer channel pin or a separated input pin ? 16-bit free-running or modulo up/down count operation ? timer system enable ? one interrupt per channel pl us terminal count interrupt 10.3.3 modes of operation in general, tpm channels may be i ndependently configured to operate in input capture, output compare, or edge-aligned pwm modes. a control bit allows the whole tpm (all ch annels) to switch to center-aligned pwm mode. when cent er-aligned pwm mode is selected, input capture, output compare, and edge-aligned pwm functions are not available on any ch annels of this tpm module. when the microcontroller is in active bdm ba ckground or bdm foreground m ode, the tpm temporarily suspends all counting until the micr ocontroller returns to normal user operating mode. during stop mode, all system clocks, including the main oscillator, are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to opera te normally. provided the tpm does not need to produce a real time reference or provide the interrupt source(s) need ed to wake the mcu from wait mode, the user can save power by disab ling tpm functions before entering wait mode. ? input capture mode when a selected edge event occurs on the associat ed mcu pin, the current va lue of the 16-bit timer counter is captured into the channel value register and an interrupt flag bit is set. rising edges, falling edges, any edge, or no edge (disable cha nnel) may be selected as the active edge which triggers the input capture. ? output compare mode when the value in the timer counter register matc hes the channel value register, an interrupt flag bit is set, and a selected output action is for ced on the associated mcu pin. the output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions).
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 165 ? edge-aligned pwm mode the value of a 16-bit modulo regist er plus 1 sets the period of the pwm output signal. the channel value register sets the duty cy cle of the pwm output signal. the user may also choose the polarity of the pwm output signal. interrupts are available at the end of the period and at the duty-cycle transition point. this type of pwm signal is calle d edge-aligned because th e leading edges of all pwm signals are aligned with the beginning of the period, which is th e same for all channels within a tpm. ? center-aligned pwm mode twice the value of a 16-bit modulo register sets the period of the pwm output, and the channel-value register sets th e half-duty-cycle duration. the timer counter counts up until it reaches the modulo value and then counts down unt il it reaches zero. as the count matches the channel value register while counting down, the pwm output becomes active. when the count matches the channel value register while countin g up, the pwm output becomes inactive. this type of pwm signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. this t ype of pwm is required for types of motors used in small appliances. this is a high-level description onl y. detailed descriptions of opera ting modes are in later sections. 10.3.4 block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn (timer channel n) where n is the channel number (1-8). the tpm shares its i/o pins with general purpos e i/o port pins (refer to i/o pin descriptions in full-chip specification for th e specific chip implementation). figure 10-2 shows the tpm structure. the central component of the tpm is the 16-bit counter that can operate as a free-running counter or a modulo up/ down counter. the tpm counter (when operating in normal up-counting mode) provides the timing referenc e for the input capture, output compare, and edge-aligned pwm functions. the timer counter mo dulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter (the values 0x0000 or 0xffff effectivel y make the counter free running). software can read the counter value at any time wi thout affecting the counti ng sequence. any write to either half of the tpmxcnt counter resets th e counter, regardless of the data value written.
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 166 freescale semiconductor figure 10-2. tpm block diagram prescale and select 16-bit comparator ps2:ps1:ps0 tof toie inter- 16-bit counter rupt logic 16-bit comparator 16-bit latch els0b els0a port channel 0 ch0ie ch0f logic inter- rupt logic cpwms ms0b ms0a counter reset clksb:clksa 31, 2, 4, 8, 16, 32, 64, bus clock fixed system clock external clock sync 16-bit comparator 16-bit latch channel 1 els1b els1a ch1ie ch1f internal bus port logic inter- rupt logic ms1b ms1a 16-bit comparator 16-bit latch channel 7 els7b els7a ch7ie ch7f port logic inter- rupt logic ms7b ms7a up to 8 channels clock source select off, bus, fixed system clock, ext or 3128 tpmxmodh:tpmxmodl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxch0 tpmxch1 tpmxc7vh:tpmxc7vl tpmxch7
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 167 the tpm channels are programmable independently as input capture, output co mpare, or edge-aligned pwm channels. alternately, the tpm can be configur ed to produce cpwm outputs on all channels. when the tpm is configured for cpwms, the counter ope rates as an up/down count er; input capture, output compare, and epwm func tions are not practical. if a channel is configured as input capture, an internal pullup device may be enabled for that channel. the details of how a module interacts w ith pin controls depends upon the ch ip implementation because the i/o pins and associated general purpose i/ o controls are not part of the modul e. refer to the di scussion of the i/o port logic in a full-chip specification. because center-aligned pwms are usually used to drive 3-phase ac-induction motors and brushless dc motors, they are typically used in sets of three or six channels. 10.4 signal description table 10-3 shows the user-accessible signals for the tpm. the number of channels may be varied from one to eight. when an external cloc k is included, it can be shared with the same pin as any tpm channel; however, it could be connected to a separate input pin. refer to the i/o pin descriptions in full-chip specification for the speci fic chip implementation. refer to documentation for the full-chip for details ab out reset states, port connections, and whether there is any pullup device on these pins. tpm channel pins can be associated with general purpose i/ o pins and have passiv e pullup devices which can be enabled with a control bit when the tpm or general purpose i/o contro ls have configured the associated pin as an input. when no tpm function is enabled to us e a corresponding pin, the pin reverts to being controlled by general purpos e i/o controls, including the port-da ta and data-direction registers. immediately after reset, no tpm functions are enabled, so all associ ated pins revert to general purpose i/o control. 10.4.1 detailed signal descriptions this section describes each user-acce ssible pin signal in detail. although table 10-3 grouped all channel pins together, any tpm pin can be sh ared with the external clock source signal. since i/o pin logic is not part of the tpm, refer to full-ch ip documentation for a specific deriva tive for more details about the interaction of tpm pin functions a nd general purpose i/o controls incl uding port data, data direction, and pullup controls. table 10-3. signal properties name function extclk 1 1 when preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. external clock source which may be selected to drive the tpm counter. tpmxchn 2 2 n=channel number (1 to 8) i/o pin associated with tpm channel n
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 168 freescale semiconductor 10.4.1.1 extclk ? external clock source control bits in the timer status a nd control register allow the user to select nothing (tim er disable), the bus-rate clock (the normal de fault source), a crystal-related clock, or an external clock as the clock which drives the tpm prescaler and s ubsequently the 16-bit tpm counter . the external clock source is synchronized in the tpm. th e bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the fre quency of the bus-rate clock, to meet nyquist criteria and allowing for jitter. the external clock signal shares the same pin as a ch annel i/o pin, so the channel pin will not be usable for channel i/o function when selected as the external cl ock source. it is the user?s responsibility to avoid such settings. if this pin is used as an external clock source (clksb :clksa = 1:1), the channel can still be used in output compare mode as a software timer (elsnb:elsna = 0:0). 10.4.1.2 tpmxchn ? tpm channel n i/o pin(s) each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the channel configuration. the tpm pins share with general purpose i/o pins , where each pin has a port data register bit, and a data di rection control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. the tpm channel does not control th e i/o pin when (elsnb:elsna = 0:0) or when (clksb:clksa = 0:0) so it normally reverts to general purpose i/ o control. when cpwms = 1 (and elsnb:elsna not = 0:0), all channels within the tpm are configured for center-aligned pwm and the tpmxchn pins are all controlled by the tpm system. when cpwms=0, the msnb:msna control bits determine whether the channel is configured for input captur e, output compare, or edge-aligned pwm. when a channel is configured for input capture (cpwms=0, msnb :msna = 0:0 and elsnb:elsna not = 0:0), the tpmxchn pin is forced to act as an e dge-sensitive input to the tpm. elsnb:elsna control bits determine what polarity edge or edges will trigger input-capture events. a synchronizer based on the bus clock is used to synchronize i nput edges to the bus cl ock. this implies the mi nimum pulse width?that can be reliably detected?on an input capture pin is four bus clock periods (with ideal cloc k pulses as near as two bus clocks can be detected). tpm uses this pi n as an input capture inpu t to override the port data and data direction controls for the same pin. when a channel is configured for output comp are (cpwms=0, msnb:msna = 0:1 and elsnb:elsna not = 0:0), the associated data di rection control is overridden, the tp mxchn pin is considered an output controlled by the tpm, and the elsnb:elsna contro l bits determine how the pin is controlled. the remaining three combinations of elsnb:elsna dete rmine whether the tpmxchn pin is toggled, cleared, or set each time the 16-bit channel valu e register matches the timer counter. when the output compare toggle mode is initially select ed, the previous value on th e pin is driven out until the next output compare event?then the pin is toggled.
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 169 when a channel is configured for edge-aligne d pwm (cpwms=0, msnb=1 and elsnb:elsna not = 0:0), the data direction is overridden, the tpmxchn pin is forced to be an output controlled by the tpm, and elsna controls the polarity of the pwm out put signal on the pin. when elsnb:elsna=1:0, the tpmxchn pin is forced high at th e start of each new period (tpmxc nt=0x0000), and the pin is forced low when the channel value register matches the timer counter. when elsna=1, the tpmxchn pin is forced low at the start of each new period (tpm xcnt=0x0000), and the pin is forced high when the channel value register matches the timer counter. figure 10-3. high-true pulse of an edge-aligned pwm figure 10-4. low-true pulse of an edge-aligned pwm chnf bit tof bit 0 ... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit 0 ... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 170 freescale semiconductor when the tpm is configur ed for center-aligned pwm (and elsnb: elsna not = 0:0), th e data direction for all channels in this tpm are overridden, the tpmxchn pins are forc ed to be outputs controlled by the tpm, and the elsna bits control the polarity of each tpmxchn output. if elsnb:elsna=1:0, the corresponding tpmxchn pin is cleared when the ti mer counter is counting up, and the channel value register matches the timer counter; the tpmxchn pin is set when the timer counter is counting down, and the channel value register matche s the timer counter. if elsna=1, th e corresponding tpmxchn pin is set when the timer counter is counting up and the chan nel value register matches the timer counter; the tpmxchn pin is cleared wh en the timer counter is counting down and the cha nnel value register matches the timer counter. figure 10-5. high-true pulse of a center-aligned pwm figure 10-6. low-true pulse of a center-aligned pwm chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 171 10.5 register definition this section consists of register descriptions in address order. a typical mcu syst em may contain multiple tpms, and each tpm may have one to eight channels, so register names include placeholder characters to identify which tpm and which channel is being refe renced. for example, tpmxcnsc refers to timer (tpm) x, channel n. tpm1c2sc would be the status and control register for channel 2 of timer 1. 10.5.1 tpm status and control register (tpmxsc) tpmxsc contains the overflow status flag and control bits used to configure the interrupt enable, tpm configuration, clock source, and prescal e factor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w0 reset00000000 figure 10-7. tpm status and control register (tpmxsc) table 10-4. tpmxsc field descriptions field description 7 tof timer overflow flag. this read/write flag is set when the tpm counter resets to 0x0000 after reaching the modulo value programmed in the tpm counter modulo register s. clear tof by reading the tpm status and control register when tof is set and then writing a logic 0 to tof. if another tpm overflow occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. this is done so a tof interrupt request cannot be lost during the clearing sequence for a previous tof. reset clears tof. writing a logic 1 to tof has no effect. 0 tpm counter has not reached modulo value or overflow 1 tpm counter has overflowed 6 toie timer overflow interrupt enable. this read/write bit enables tpm overflow interrupts. if toie is set, an interrupt is generated when tof equals one. reset clears toie. 0 tof interrupts inhibited (use for software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select. when present, this read/wri te bit selects cpwm operating mode. by default, the tpm operates in up-counting mode for input capture, out put compare, and edge-aligned pwm functions. setting cpwms reconfigures the tpm to operate in up/down counting mode for cpwm functions. reset clears cpwms. 0 all channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each ch annel?s status and control register. 1 all channels operate in center-aligned pwm mode.
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 172 freescale semiconductor 10.5.2 tpm-counter regist ers (tpmxcnth:tpmxcntl) the two read-only tpm counter regist ers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until th e other half is read. this allows coherent 16-bit reads in either big-endian or little-endian order which makes th is more friendly to various comp iler implementations. the coherency mechanism is automatically restarted by an mcu reset or any write to the time r status/control register (tpmxsc). 4?3 clks[b:a] clock source selects. as shown in table 10-5 , this 2-bit field is used to disabl e the tpm system or select one of three clock sources to drive the counter prescaler. the fixed system clock source is only meaningful in systems with a pll-based or fll-based system cl ock. when there is no pll or fll, the fixed-system clock source is the same as the bus rate clock. the external source is synchronized to the bus clock by tpm module, and the fixed system clock source (when a pll or fll is present) is synchronized to the bus clock by an on-chip synchronization circuit. when a pll or fll is present but not e nabled, the fixed-system clock source is the same as the bus-rate clock. 2?0 ps[2:0] prescale factor select. this 3-bit field selects one of 8 division factors for the tpm clock input as shown in ta b l e 1 0 - 6 . this prescaler is located after any clock source syn chronization or clock source selection so it affects the clock source selected to drive the tpm system. the new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. table 10-5. tpm-clock-source selection clksb:clksa tpm clock so urce to prescaler input 00 no clock selected (tpm counter disable) 01 bus rate clock 10 fixed system clock 11 external source table 10-6. prescale factor selection ps2:ps1:ps0 tpm clock source divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 table 10-4. tpmxsc field descriptions (continued) field description
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 173 reset clears the tpm count er registers. writing a ny value to tpmxcnth or tpmxcntl also clears the tpm counter (tpmxcnth:tpmxcntl) and resets the coherency mechanism, regardless of the data involved in the write. when bdm is active, the time r counter is frozen (this is the value that will be re ad by user); the coherency mechanism is frozen such that the buffer latches rema in in the state they were in when the bdm became active, even if one or both counter halves are read whil e bdm is active. this assu res that if the user was in the middle of reading a 16- bit register when bdm beca me active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. in bdm mode, writing any value to tpmxsc, tpmx cnth or tpmxcntl registers resets the read coherency mechanism of the tpmxcn th:l registers, regardless of the data involved in the write. 10.5.3 tpm counter modulo re gisters (tpmxmodh:tpmxmodl) the read/write tpm modulo regist ers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock, and the overflow flag (tof) becomes set. writing to tpmxmodh or tpmxmodl i nhibits the tof bit and overflow interrupts until the other byte is written. reset sets the tp m counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). writing to either byte (tpmxmodh or tpmxmodl) latches the value into a buffer and the registers are updated with the value of their write buffer acco rding to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), then the registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), then the registers are updated after both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff the latching mechanism may be ma nually reset by writing to the tp mxsc address (w hether bdm is active or not). 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter reset00000000 figure 10-8. tpm counter register high (tpmxcnth) 76543210 rbit 7654321bit 0 w any write to tpmxcntl clears the 16-bit counter reset00000000 figure 10-9. tpm counter register low (tpmxcntl)
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 174 freescale semiconductor when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxsc register) such that the buffer latches remain in the state they were in when the bdm becam e active, even if one or both halves of the modulo register are written while bdm is active. a ny write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while bdm is active. reset the tpm counter before writin g to the tpm modulo registers to a void confusion about when the first counter overflow will occur. 10.5.4 tpm channel n status an d control register (tpmxcnsc) tpmxcnsc contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 10-10. tpm counter modulo register high (tpmxmodh) 76543210 r bit 7654321bit 0 w reset00000000 figure 10-11. tpm counter modulo register low (tpmxmodl) 76543210 rchnf chnie msnb msna elsnb elsna 00 w0 reset00000000 = unimplemented or reserved figure 10-12. tpm channel n status and control register (tpmxcnsc)
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 175 table 10-7. tpmxcnsc field descriptions field description 7 chnf channel n flag. when channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. when channel n is an output com pare or edge-aligned/center-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. when channel n is an edge-aligned/center-aligned pwm channel and the duty cycle is set to 0% or 100%, chnf will not be set even when the value in the tpm counter registers ma tches the value in the tpm channel n value registers. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a logic 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf remains set after the clear sequence completed for the earlier chnf. this is done so a chnf interr upt request cannot be lost due to clearing a previous chnf. reset clears the chnf bit. writing a logic 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event on channel n 6 chnie channel n interrupt enable. this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use for software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n. when cpwms=0, ms nb=1 configures tpm channel n for edge-aligned pwm mode. refer to the summary of channel mode and setup controls in table 10-8 . 4 msna mode select a for tpm channel n. when cpwms=0 and msnb=0, msna configures tpm channel n for input-capture mode or output compare mode. refer to ta bl e 1 0 - 8 for a summary of channel mode and setup controls. note: if the associated port pin is not stable for at least two bus cl ock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3?2 elsnb elsna edge/level select bits. depending upon the operating mo de for the timer channel as set by cpwms:msnb:msna and shown in table 10-8 , these bits select the polarity of the input e dge that triggers an input capture event, select the level that will be driven in response to an output co mpare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 configures the related timer pin as a general purpose i/o pin not related to any timer functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. table 10-8. mode, edge, and level selection cpwms msnb:msna elsnb:el sna mode configuration x xx 00 pin not used for tpm - revert to general purpose i/o or other peripheral control
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 176 freescale semiconductor 10.5.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) these read/write register s contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pw m functions. the channel registers are cleared by reset. in input capture mode, reading eith er byte (tpmxcnvh or tpmxcnvl) la tches the contents of both bytes into a buffer where they remain latched until the othe r half is read. this latc hing mechanism also resets 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 00 output compare software compare only 01 toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 10-13. tpm channel value register high (tpmxcnvh) 76543210 r bit 7654321bit 0 w reset00000000 figure 10-14. tpm channel value register low (tpmxcnvl) table 10-8. mode, edge, and level selection cpwms msnb:msna elsnb:el sna mode configuration
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 177 (becomes unlatched) when the tpmxcnsc register is wr itten (whether bdm mode is active or not). any write to the channel registers will be ignored during the input capture mode. when bdm is active, the coherency mechanism is fro zen (unless reset by writi ng to tpmxcnsc register) such that the buffer latches remain in the state they were in when the bdm becam e active, even if one or both halves of the channel register are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. the value read from the tpmxcnvh and tpmxcnvl registers in bdm mode is the value of these registers and not the value of their read buffer. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. after both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of clksb:clksa bits and the selected mode, so: ? if (clksb:clksa = 0:0), then the registers are updated when the second byte is written. ? if (clksb:clksa not = 0:0 and in output compar e mode) then the registers are updated after the second byte is written and on the next change of the tpm counter (end of the prescaler counting). ? if (clksb:clksa not = 0:0 and in epwm or cpwm modes), then the registers are updated after the both bytes were written, and the tpm count er changes from (tpm xmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if th e tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. the latching mechanism may be ma nually reset by writing to the tp mxcnsc register (whether bdm mode is active or not). this latchi ng mechanism allows cohe rent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. when bdm is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active even if one or both halves of the channel register are written while bdm is active. any write to the channel regist ers bypasses the buffer latche s and directly write to the channel register while bdm is act ive. the values written to the ch annel register while bdm is active are used for pwm & output compare operation once nor mal execution resumes. writes to the channel registers while bdm is acti ve do not interfere with partial comple tion of a coherency sequence. after the coherency mechanism has been fully exercised, the channel registers ar e updated using the buffered values written (while bdm was not active) by the user. 10.6 functional description all tpm functions are associ ated with a central 16-bit counter which allows flex ible selection of the clock source and prescale factor. there is also a 16-bit modulo register associated with the main counter. the cpwms control bit chooses be tween center-aligned pwm operation for all channels in the tpm (cpwms=1) or general purpose ti ming functions (cpwms=0) where each channel can independently be configured to operate in input capture, output co mpare, or edge-aligned pwm mode. the cpwms control bit is located in the main tpm status and control regi ster because it affects all channels within the tpm and influences the wa y the main counter operates. (in cpwm m ode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.)
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 178 freescale semiconductor the following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend upon the opera ting mode, these topics will be covered in the associated mode explanation sections. 10.6.1 counter all timer functions are based on the main 16-bi t counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, end-of-count overflow, up- counting vs. up/down counting, and manual counter reset. 10.6.1.1 counter clock source the 2-bit field, clksb:clksa, in the timer status a nd control register (tpmxs c) selects one of three possible clock sources or off (which effectively disabl es the tpm). see table 10-5 . after any mcu reset, clksb:clksa=0:0 so no clock source is selected, and the tpm is in a very low power state. these control bits may be read or writ ten at any time and disabling the timer (writing 00 to the clksb:clksa field) does not affect the values in the counter or other timer registers. the bus rate clock is the main system bus cl ock for the mcu. this clock source requires no synchronization because it is the clock that is used for all inte rnal mcu activities including operation of the cpu and buses. in mcus that have no pll and fll or the pll and fll are not engage d, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. when a pll or fll is present and engaged, a synchronize r is required between the crystal di vided-by two clock source and the timer counter so counter transitions will be properly aligne d to bus-clock transiti ons. a synchronizer will be used at chip level to s ynchronize the crystal-related source clock to the bus clock. the external clock source may be connected to any tpm ch annel pin. this clock s ource always has to pass through a synchronizer to assure that counter transitions ar e properly aligned to bus clock transitions. the bus-rate clock drives the synchronizer; therefore, to meet nyquist criter ia even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by f our. with ideal clocks the external clock can be as fast as bus clock divided by four. when the external clock source shar es the tpm channel pin, this pin s hould not be used for other channel timing functions. for example, it w ould be ambiguous to configure channel 0 for input capture when the tpm channel 0 pin was also being used as the timer external clock source . (it is the user?s responsibility table 10-9. tpm clock source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (t pm counter disabled) 01 bus rate clock 10 fixed system clock 11 external source
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 179 to avoid such settings.) the tpm channel could still be used in output compare mode for software timing functions (pin controls set not to affect the tpm channel pin). 10.6.1.2 counter overflow and modulo reset an interrupt flag and enable are associated wi th the 16-bit main counter. the flag (tof) is a software-accessible indication that the timer counter has overflowed. th e enable signal selects between software polling (toie=0) where no hardware interrupt is gene rated, or interrupt-driven operation (toie=1) where a static hardware interrupt is generated whenever the tof flag is equal to one. the conditions causing tof to become set depend on whether the tpm is configured for center-aligned pwm (cpwms=1). in the simplest mode, there is no modulus limit and the tpm is not in cpwms=1 mode. in this case, the 16-bit timer counter counts from 0x0000 th rough 0xffff and overflows to 0x0000 on the next counting clock. tof be comes set at the transition fr om 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the tpm is in center-aligned pwm mode (cpwms=1), the tof flag ge ts set as the counter changes direction at the end of the count valu e set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). this corresponds to the end of a pwm period (the 0x0000 count value corresponds to the center of a period). 10.6.1.3 counting modes the main timer counter has two c ounting modes. when center-aligned pwm is selected (cpwms=1), the counter operates in up/down counting mode. otherwise, the counter operates as a simple up counter. as an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is specified, th e counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up count ing. both 0x0000 and th e terminal count value are normal length counts (one tim er clock period long). in this m ode, the timer overflow flag (tof) becomes set at the end of the terminal-count period (a s the count changes to the next lower count value). 10.6.1.4 manual counter reset the main timer counter can be manually reset at any time by writing any value to either half of tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only half of the counter wa s read before resetting the count. 10.6.2 channel mode selection provided cpwms=0, the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corr esponding channel. choices include input capture, output compare, and edge-aligned pwm.
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 180 freescale semiconductor 10.6.2.1 input capture mode with the input-capture function, the tpm can capture th e time at which an exte rnal event occurs. when an active edge occurs on the pin of an input-capture channel, the tpm latches the contents of the tpm counter into the channel-value registers (tpmxcnvh: tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. in input capture mode, the tpmxcnvh and tpmxcnvl registers are read only. when either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endi an or little-endian order. the coherency sequence can be manually reset by writing to the channel st atus/control register (tpmxcnsc). an input capture event sets a flag bit (chnf) wh ich may optionally generate a cpu interrupt request. while in bdm, the input ca pture function works as conf igured by the user. when an external event occurs, the tpm latches the contents of the tpm counter (whi ch is frozen because of the bdm mode) into the channel value registers and sets the flag bit. 10.6.2.2 output compare mode with the output-compare function, the tpm can ge nerate timed pulses with programmable position, polarity, duration, and frequency. when the counter reach es the value in the channel-value registers of an output-compare channel, the tpm can se t, clear, or toggle the channel pin. in output compare mode, values are transferred to th e corresponding timer channel re gisters only after both 8-bit halves of a 16-bit register ha ve been written and according to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated at the ne xt change of the tpm counter (end of the prescaler counting) after the second byte is written. the coherency sequence can be manually reset by wr iting to the channel st atus/control register (tpmxcnsc). an output compare event sets a flag bit (chnf) wh ich may optionally generate a cpu-interrupt request. 10.6.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counti ng mode of the timer c ounter (cpwms=0) and can be used when other channels in the same tpm ar e configured for input cap ture or output compare functions. the period of this pwm signal is dete rmined by the value of the modulus register (tpmxmodh:tpmxmodl) plus 1. the duty cycle is determined by the setting in the timer channel register (tpmxcnvh:tpmxcn vl). the polarity of this pwm signal is determined by the setting in the elsna control bit. 0% and 100% duty cycle cases are possible. the output compare value in the tpm channel register s determines the pulse wi dth (duty cycle) of the pwm signal ( figure 10-15 ). the time between the modulus overflo w and the output compare is the pulse width. if elsna=0, the counter overflow forces the pwm signal high, and the out put compare forces the pwm signal low. if elsna=1, the c ounter overflow forces the pwm si gnal low, and the output compare forces the pwm signal high.
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 181 figure 10-15. pwm period and pulse width (elsna=0) when the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel regi ster (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting. this implies that the modulus setting must be less than 0xffff in order to get 100% duty cycle. because the tpm may be used in an 8-bit mcu, the se ttings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxcnvh and tpmxcnvl, actually wr ite to buffer registers. in e dge-aligned pwm mode, values are transferred to the corresponding timer- channel registers according to th e value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a fr ee-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. 10.6.2.4 center-aligned pwm mode this type of pwm output uses th e up/down counting mode of the timer counter (cpwms=1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal while the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff becaus e values outside this ra nge can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) period = 2 x (tpmxmodh:tpmxmodl ); tpmxmodh:tpmxmodl=0x0001-0x7fff if the channel-value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if you do not need to generate 100% duty cycle). this is not a significant limitation. the resu lting period would be much longer than require d for normal applications. tpmxmodh:tpmxmodl=0x0000 is a special case that should not be used wi th center-aligned pwm mode. when cpwms=0, this case co rresponds to the counter runni ng free from 0x0000 through 0xffff, but when cpwms=1 the counter needs a valid match to the modulus register so mewhere other than at 0x0000 in order to change directions from up-counting to down-counting. period pulse width overflow overflow overflow output compare output compare output compare tpmxchn
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 182 freescale semiconductor the output compare value in the tpm channel registers (times 2) determines the pulse width (duty cycle) of the cpwm signal ( figure 10-16 ). if elsna=0, a compare occurred while counting up forces the cpwm output signal low and a compare occurred while counting down forc es the output high. the counter counts up until it reaches the modulo se tting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure 10-16. cpwm period and pulse width (elsna=0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also require d for some types of motor drives. input capture, output compare, a nd edge-aligned pwm functi ons do not make sense when the counter is operating in up/down counting mode so th is implies that all act ive channels within a tpm must be used in cpwm mode when cpwms=1. the tpm may be used in an 8-bit mc u. the settings in the timer channe l registers are buffered to ensure coherent 16-bit updates and to a void unexpected pwm pulse widths. wr ites to any of the registers tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl , actually write to buffer registers. in center-aligned pwm mode, the tpmxcnvh:l registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff. when tpmxcnth:tpmxcntl=tpmxmodh:tpmxmodl, the tpm can optionally generate a tof interrupt (at the end of this count). writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo re gisters. writing to tpmxcnsc ca ncels any values written to the channel value registers and resets the c oherency mechanism for tpmxcnvh:tpmxcnvl. period pulse width count= count= 0 count= output compare (count down) output compare (count up) tpmxchn 2 x tpmxmodh:tpmxmodl 2 x tpmxcnvh:tpmxcnvl tpmxmodh:tpmxmodl tpmxmodh:tpmxmodl
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 183 10.7 reset overview 10.7.1 general the tpm is reset whenever any mcu reset occurs. 10.7.2 description of reset operation reset clears the tpmxsc register wh ich disables clocks to the tpm a nd disables timer overflow interrupts (toie=0). cpwms, msnb, msna, elsnb, and elsna are all cleared which configures all tpm channels for input-capture operation with the associated pins disconnect ed from i/o pin logic (so all mcu pins related to the tpm revert to general purpose i/o pins). 10.8 interrupts 10.8.1 general the tpm generates an optional interr upt for the main counter overflow a nd an interrupt for each channel. the meaning of channel interrupts depends on each channel?s mode of operation. if the channel is configured for input capture, the in terrupt flag is set ea ch time the selected input capture edge is recognized. if the channel is configur ed for output compare or pwm modes, the interrupt flag is set each time the main timer counter matches the va lue in the 16-bit channel value register. all tpm interrupts are listed in table 10-10 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the tpm and getting r ecognized by the separate interrupt processing logic. the tpm module will provide a high-tr ue interrupt signal. vectors and pr iorities are determined at chip integration time in the interrupt module so refer to the user?s guide for th e interrupt module or to the chip?s complete document ation for details. 10.8.2 description of interrupt operation for each interrupt source in the tpm, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input captur e, or output-compare events. this flag may be read (polled) by software to determine that the action has occurred, or an associated enab le bit (toie or chnie) can be set table 10-10. interrupt summary interrupt local enable source description tof toie counter overflow set each time th e timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) chnf chnie channel event an input capt ure or output compare event took place on channel n
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 184 freescale semiconductor to enable hardware interrupt generati on. while the interrupt enable bit is se t, a static interr upt will generate whenever the associated interrupt flag equals one. the user?s software must perform a sequence of steps to clear the interrupt flag before retu rning from the interrupt-service routine. tpm interrupt flags are clear ed by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to th e bit. if a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 10.8.2.1 timer overflow in terrupt (tof) description the meaning and details of operation for tof inte rrupts varies slightly depending upon the mode of operation of the tpm system (gen eral purpose timing functions vers us center-aligned pwm operation). the flag is cleared by the two step sequence described above. 10.8.2.1.1 normal case normally tof is set when the timer counter ch anges from 0xffff to 0x0000. when the tpm is not configured for center-aligned pwm (cpwms=0), tof ge ts set when the timer c ounter changes from the terminal count (the value in th e modulo register) to 0x0000. this case corresponds to the normal meaning of counter overflow. 10.8.2.1.2 center-aligned pwm case when cpwms=1, tof gets set when the timer c ounter changes directi on from up-counting to down-counting at the end of the term inal count (the value in the modul o register). in this case the tof corresponds to the end of a pwm period. 10.8.2.2 channel event interrupt description the meaning of channel interrupts depends on the channel?s current m ode (input-capture, output-compare, edge-aligned pwm, or center-aligned pwm). 10.8.2.2.1 input capture events when a channel is configured as an input capture channel, the elsnb:e lsna control bits select no edge (off), rising edges, falling edges or any edge as the ed ge which triggers an input capture event. when the selected edge is detected, the interrupt flag is set. the flag is cleared by the two-step sequence described in section 10.8.2, ?description of interrupt operation . ? 10.8.2.2.2 output compare events when a channel is configured as an output compare chan nel, the interrupt flag is set each time the main timer counter matches the 16-bit valu e in the channel value register. th e flag is cleared by the two-step sequence described section 10.8.2, ?description of interrupt operation . ?
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 185 10.8.2.2.3 pwm end-of-duty-cycle events for channels configured for pwm operation there are two possibilities. when th e channel is configured for edge-aligned pwm, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. wh en the channel is configured for center-aligned pwm, the timer count matches the channel value regi ster twice during each pwm cycle. in this cpwm case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value regi ster. the flag is cleared by the two-step sequence described section 10.8.2, ?description of interrupt operation . ? 10.9 the differences from tpm v2 to tpm v3 1. write to tpmxcnth:l registers ( section 10.5.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) ) [se110-tpm case 7] any write to tpmxcnth or tpmxcntl regi sters in tpm v3 clears the tpm counter (tpmxcnth:l) and the prescaler co unter. instead, in the tpm v2 only the tpm counter is cleared in this case. 2. read of tpmxcnth:l registers ( section 10.5.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) ) ? in tpm v3, any read of tpmxcnth:l register s during bdm mode returns the value of the tpm counter that is frozen. in tpm v2, if only one byte of th e tpmxcnth:l registers was read before the bdm mode became active, th en any read of tpmxcnth:l registers during bdm mode returns the latched value of tpmxcn th:l from the read buffer instead of the frozen tpm counter value. ? this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxsc, tpmxcnth or tpmxcntl. instead, in these conditions the tpm v2 does not clear this read coherency mechanism. 3. read of tpmxcnvh:l registers ( section 10.5.5, ?tpm channel value registers (tpmxcnvh:tpmxcnvl) ) ? in tpm v3, any read of tpmxcnvh:l register s during bdm mode returns the value of the tpmxcnvh:l register. in tpm v2, if only one byte of the tpmxcnvh:l registers was read before the bdm mode became active, then a ny read of tpmxcnvh:l registers during bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the value in the tpmxcnvh:l registers. ? this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxcnsc. instead, in this condition the tp m v2 does not clear this read coherency mechanism. 4. write to tpmxcnvh:l registers ? input capture mode ( section 10.6.2.1, ?input capture mode ) in this mode the tpm v3 does not allow the wr ites to tpmxcnvh:l registers. instead, the tpm v2 allows these writes. ? output compare mode ( section 10.6.2.2, ?output compare mode ) in this mode and if (clksb:clksa not = 0:0), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer at the next change of the tpm counter (end of the
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 186 freescale semiconductor prescaler counting) after the se cond byte is written. instead, the tpm v2 always updates these registers when their second byte is written. the following procedure can be used in the tpm v3 to verify if the tpmxcnvh:l registers were updated with the new value th at was written to these register s (value in their write buffer). ... write the new value to tpmxcnvh:l; read tpmxcnvh and tpmxcnvl registers; while (the read value of tp mxcnvh:l is different from the new value written to tpmxcnvh:l) begin read again tpmxcnvh and tpmxcnvl; end ... in this point, the tpmxcnvh:l registers were updated, so the program can continue and, for example, write to tpmxc0sc without can celling the previous write to tpmxcnvh:l registers. ? edge-aligned pwm ( section 10.6.2.3, ?edge-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer af ter that the both bytes we re written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to $0000. ? center-aligned pwm ( section 10.6.2.4, ?center-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer af ter that the both bytes we re written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to (tpmxmodh:l - 1). 5. center-aligned pwm ( section 10.6.2.4, ?center-aligned pwm mode ) ? tpmxcnvh:l = tpmxmodh:l [se110-tpm case 1] in this case, the tpm v3 produces 100% duty cycle. instead, the tpm v2 produces 0% duty cycle. ? tpmxcnvh:l = (tpmxmodh:l - 1) [se110-tpm case 2] in this case, the tpm v3 produc es almost 100% duty cycle. in stead, the tpm v2 produces 0% duty cycle. ? tpmxcnvh:l is changed from 0x0000 to a non-zero value [se110-tpm case 3 and 5] in this case, the tpm v3 waits for the start of a new pwm period to be gin using the new duty cycle setting. instead, the tpm v2 changes the channel output at the middle of the current pwm period (when the count reaches 0x0000).
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 187 ? tpmxcnvh:l is changed from a non-zero value to 0x0000 [se110-tpm case 4] in this case, the tpm v3 finishes the curren t pwm period using the old duty cycle setting. instead, the tpm v2 finishes the current pw m period using the new duty cycle setting. 6. write to tpmxmodh:l re gisters in bdm mode ( section 10.5.3, ?tpm counter modulo registers (tpmxmodh:tpmxmodl) ) in the tpm v3 a write to tpmxsc register in bdm mode clears the write coherency mechanism of tpmxmodh:l registers. instead, in the tpm v2 this coherency mechanism is not cleared when there is a write to tpmxsc register. 7. update of epwm signal when clksb:clksa = 00 in the tpm v3 if clksb:clksa = 00, then the ep wm signal in the channel output is not update (it is frozen while clksb:clksa = 00). instead , in the tpm v2 the epwm signal is updated at the next rising edge of bus clock af ter a write to tpmxcnsc register. the figure 10-17 and figure 10-18 show when the epwm signals generated by tpm v2 and tpm v3 after the reset (clksb:clksa = 00) and if there is a write to tpmxcnsc register. figure 10-17. generation of high-true epwm signal by tpm v2 and v3 after the reset elsnb:elsna bits clksb:clksa bits 0 tpmxmodh:tpmxmodl = 0x0007 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmv2 tpmxchn epwm mode 00 00 10 bus clock 01 1234567 01 2 chnf bit msnb:msna bits 00 10 (in tpmv2 and tpmv3) tpmv3 tpmxchn ... reset (active low)
timer/pwm module (s08tpmv3) mc9s08ac16 series data sheet, rev. 8 188 freescale semiconductor figure 10-18. generation of low-true epwm signal by tpm v2 and v3 after the reset the following procedure can be used in tpm v3 (when the channel pin is also a port pin) to emulate the high-true epwm generated by tpm v2 after the reset. ... configure the channel pin as output port pin and set the output pin; configure the channel to generate the epwm signal but keep elsnb:elsna as 00; configure the other registers (tpmxmo dh, tpmxmodl, tpmxcnvh, tpmxcnvl, ...); configure clksb:clksa bits (tpm v3 starts to generate the high-true epwm signal, however tpm does not control the channel pin, so the epwm signal is not available); wait until the tof is set (or use the tof interrupt); enable the channel output by configuring elsnb: elsna bits (now epwm signal is available); ... elsnb:elsna bits clksb:clksa bits 0 tpmxmodh:tpmxmodl = 0x0007 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmv2 tpmxchn epwm mode 00 00 01 bus clock 01 1234567 01 2 chnf bit msnb:msna bits 00 10 (in tpmv2 and tpmv3) tpmv3 tpmxchn ... reset (active low)
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 189 chapter 11 serial communications interface (s08sciv4) 11.1 introduction the mc9s08ac16 series includes two independent serial communications interface (sci) modules which are sometimes called univers al asynchronous receiver/ transmitters (uarts). typically, these systems are used to connect to the rs232 serial input/output (i/o ) port of a persona l computer or workstation, but they can also be used to communicate with othe r embedded controllers. a flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kbaud. transmit and receive within the same sci use a common baud rate, and each sci module has a separate baud rate generator. this sci system offers many adva nced features not commonly found on other asynchronous serial i/o peripherals on other embedded cont rollers. the receiver employs an advanced data sampling technique that ensures reliable communicati on and noise detection. hardware parity, receiver wakeup, and double buffering on transmit and r eceive are also included. note ignore any references to stop1 low-power mode in th is chapter, because the mc9s08ac16 series does not support it.
chapter 11 serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 190 freescale semiconductor figure 11-1. mc9s08ac16 block diagram highlighting the sci ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 191 11.1.1 features features of sci module include: ? full-duplex, standard non-re turn-to-zero (nrz) format ? double-buffered transmitter and re ceiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing erro r, and noise error ? idle receiver detect ? active edge on receive pin ? break detect supporting lin ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver wakeup by idle-line or address-mark ? optional 13-bit break character generati on / 11-bit break character detection ? selectable transmitt er output polarity 11.1.2 modes of operation see section 11.3, ?functional description ,? for details concerning sci operation in these modes: ? 8- and 9-bit data modes ? stop mode operation ? loop mode ? single-wire mode
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 192 freescale semiconductor 11.1.3 block diagram figure 11-2 shows the transmitter portion of the sci. figure 11-2. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd txinv brk13
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 193 figure 11-3 shows the receiver portion of the sci. figure 11-3. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rxinv lbkde rwuid
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 194 freescale semiconductor 11.2 register definition the sci has eight 8-bit registers to control baud ra te, select sci options, re port sci status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. 11.2.1 sci baud rate regi sters (scixbdh, scixbdl) this pair of registers co ntrols the prescale diviso r for sci baud rate genera tion. to update the 13-bit baud rate setting [sbr12:sbr0], first writ e to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate genera tor remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scix c2 are written to 1). 76543210 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset00000000 = unimplemented or reserved figure 11-4. sci baud rate register (scixbdh) table 11-1. scixbdh field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif flag is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif flag is 1. 4:0 sbr[12:8] baud rate modulo divisor ? the 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 1 - 2 . 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset00000100 figure 11-5. sci baud rate register (scixbdl)
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 195 11.2.2 sci control register 1 (scixc1) this read/write register is used to contro l various optional features of the sci system. table 11-2. scixbdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ? these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 1 - 1 . 76543210 r loops sciswai rsrc m wake ilt pe pt w reset00000000 figure 11-6. sci control register 1 (scixc1) table 11-3. scixc1 field descriptions field description 7 loops loop mode select ? selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ? rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter output s are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 6 sciswai sci stops in wait mode 0 sci clocks continue to run in wait mode so the sci c an be the source of an interrupt that wakes up the cpu. 1 sci clocks freeze while cpu is in wait mode. 5 rsrc receiver source select ? this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connecte d to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ? start + 8 data bits (lsb first) + stop. 1 receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. 3 wake receiver wakeup method select ? refer to section 11.3.3.2, ?recei ver wakeup operation ? for more information. 0 idle-line wakeup. 1 address-mark wakeup. 2 ilt idle line type select ? setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. refer to section 11.3.3.2.1, ?idle-line wakeup ? for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit.
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 196 freescale semiconductor 11.2.3 sci control register 2 (scixc2) this register can be read or written at any time. 1 pe parity enable ? enables hardware parity generation and checking. when parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treat ed as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type ? provided parity is enabled (pe = 1), this bit sele cts even or odd parity. odd parity means the total number of 1s in the data character, including the parity bi t, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 0 even parity. 1 odd parity. 76543210 r tie tcie rie ilie te re rwu sbk w reset00000000 figure 11-7. sci control register 2 (scixc2) table 11-4. scixc2 field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre flag is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc flag is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf flag is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle flag is 1. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 11.3.2.1, ?send break and queued idle ? for more details. when te is written to 0, the transmitt er keeps control of the port txd pi n until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. table 11-3. scixc1 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 197 11.2.4 sci status register 1 (scixs1) this register has eight read-only st atus flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. 2 re receiver enable ? when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on. 1 rwu receiver wakeup control ? this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 11.3.3.2, ?rec eiver wakeup operation ? for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wakeup condition. 0 sbk send break ? writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relati ve to the information currently being transmitted, a second break character may be queued before software clears sbk. refer to section 11.3.2.1, ?send break and queued idle ? for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. 76543210 r tdre tc rdrf idle or nf fe pf w reset11000000 = unimplemented or reserved figure 11-8. sci status register 1 (scixs1) table 11-4. scixc2 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 198 freescale semiconductor table 11-5. scixs1 field descriptions field description 7 tdre transmit data register empty flag ? tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving r oom for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ? tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmi ssion activity complete). tc is cleared automatically by read ing scixs1 with tc = 1 and then doing one of the following three things: ? write to the sci data register (scixd) to transmit new data ? queue a preamble by changing te from 0 to 1 ? queue a break character by writing 1 to sbk in scixc2 5 rdrf receive data register full flag ? rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ? idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn?t start counting idle bit times until after the stop bit. so th e stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag ? or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost bec ause there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag ? the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if an y of these samples disagrees with the rest of the samples within any bit time in the frame, the flag nf will be set at the same time as the flag rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 0 no noise detected. 1 noise detected in the received character in scixd.
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 199 11.2.5 sci status register 2 (scixs2) this register has one read-only status flag. 1 fe framing error flag ? fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ? pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 0 no parity error. 1 parity error. 76543210 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf w reset00000000 = unimplemented or reserved figure 11-9. sci status register 2 (scixs2) table 11-6. scixs2 field descriptions field description 7 lbkdif lin break detect interrupt flag ? lbkdif is set when the lin break detect circuitry is enabled and a lin break character is detected. lbkdif is cleared by writing a ?1? to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ? rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ?1? to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv 1 receive data inversion ? setting this bit reverses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect ? rwuid controls whether the idle charac ter that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length ? brk13 is used to select a longer transmitted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is transmitted with length of 10 bit times (11 if m = 1) 1 break character is transmitted with length of 13 bit times (14 if m = 1) table 11-5. scixs1 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 200 freescale semiconductor when using an internal oscillator in a lin system, it is necessary to raise the break det ection threshold by one bit time. under the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slav e which is running 14% faster than the master. this would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing errors are inhibited and the break detectio n threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 11.2.6 sci control register 3 (scixc3) 1 lbkde lin break detection enable ? lbkde is used to select a longer break character detection length. while lbkde is set, framing error (fe) and receive data regi ster full (rdrf) flags are prevented from setting. 0 break character is detected at length of 10 bit times (11 if m = 1). 1 break character is detected at length of 11 bit times (12 if m = 1). 0 raf receiver active flag ? raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status flag can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). 1 setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. 76543210 rr8 t8 txdir txinv orie neie feie peie w reset00000000 = unimplemented or reserved figure 11-10. sci control register 3 (scixc3) table 11-7. scixc3 field descriptions field description 7 r8 ninth data bit for receiver ? when the sci is configured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered da ta in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd complete s automatic flag clearing sequences which could allow r8 and scixd to be overwritten with new data. 6 t8 ninth data bit for transmitter ? when the sci is configured for 9-bit da ta (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd regi ster. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after scixd is written so t8 should be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. 5 txdir txd pin direction in single-wire mode ? when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines t he direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. table 11-6. scixs2 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 201 11.2.7 sci data register (scixd) this register is actually two separate registers. r eads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and wr ites of this register are also involved in the automatic flag clearing mechanisms for the sci status flags. 11.3 functional description the sci allows full-duplex, as ynchronous, nrz serial communica tion among the mcu and remote devices, including other mcus. the sc i comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver opera te independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following desc ribes each of the blocks of the sci. 11.3.1 baud rate generation as shown in figure 11-12 , the clock source for the sci baud ra te generator is the bus-rate clock. 4 txinv 1 transmit data inversion ? setting this bit reverses the pola rity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted 3 orie overrun interrupt enable ? this bit enables the overrun flag (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ? this bit enables the noise flag (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ? this bit enables the framing error flag (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ? this bit enables the parity error flag (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. 1 setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. 76543210 rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 reset00000000 figure 11-11. sci data register (scixd) table 11-7. scixc3 field descriptions (continued) field description
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 202 freescale semiconductor figure 11-12. sci baud rate generation sci communications require the transmitter and re ceiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolera nce on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundari es on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a sci sy stem whose bus frequency is driven by a crystal, the allowed baud rate mismatch is a bout 4.5 percent for 8-bit data form at and about 4 percent for 9-bit data format. although baud rate modulo divider sett ings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 11.3.2 transmitter functional description this section describes the overall block diagram for th e sci transmitter, as well as specialized functions for sending break and idle characters. the transmitter block diagram is shown in figure 11-2 . the transmitter output (txd) idle st ate defaults to logic high (txinv = 0 following reset). the transmitter output is inverted by setting txinv = 1. the transmitter is enabled by se tting the te bit in scixc2. this queues a preamble character that is one full character fr ame of the idle state. th e transmitter then remains idle until data is available in the tr ansmit data buffer. progr ams store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmit ter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the m control bit. for th e remainder of this section, we will assume m = 0, selecting the normal 8-bi t data mode. in 8-bit data m ode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmit data register is transfer red to the shift register (synchronized with the ba ud rate clock) and the transmit data register empt y (tdre) status flag is set to indicate another character may be written to the transmit data buffer at scixd. if no new character is waiting in th e transmit data buffer after a stop bit is shifted out the txd pin, the transmitter sets the transmit comp lete flag and enters an idle m ode, with txd high, waiting for more characters to transmit. sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 203 writing 0 to te does not immediately release the pin to be a general-pur pose i/o pin. any tr ansmit activity that is in progress must first be completed. this includes data characters in progress, queued idle characters, and queued break characters. 11.3.2.1 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer break of 13 bit times can be enabled by setting brk13 = 1. normally, a program would wait for tdre to become se t to indicate the last ch aracter of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is avai lable. if sbk is st ill 1 when the queue d break moves into the shifter (synchronized to the baud ra te clock), an additional break char acter is queued. if the receiving device is another sci, the break charact ers will be received as 0s in all eight data bits a nd a framing error (fe = 1) occurs. when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifte r, then write 0 and then write 1 to the te bit. this action queues an idle ch aracter to be sent as soon as the shifter is available. as long as the character in the shifter does not finish while te = 0, th e sci transmitter never actually re leases control of the txd pin. if there is a possibility of the shifter finishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affect ed by the brk13 and m bits as shown below. 11.3.3 receiver functional description in this section, the r eceiver block diagram ( figure 11-3 ) is used as a guide for the overall receiver functional description. next, the data sampling technique used to reconstruc t receiver data is described in more detail. finally, two variations of the receiver wakeup function are explained. the receiver input is inverted by setting rxinv = 1. the receiver is enabled by setting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine ) data bits (lsb first), and a stop bit of logic 1. for information a bout 9-bit data mode, refer to section 11.3.5.1, ?8- and 9-bit data modes .? for the remainder of this discu ssion, we assume the sci is confi gured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive da ta register and the receive data register full (rdrf) table 11-8. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 204 freescale semiconductor status flag is set. if rd rf was already se t indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. because the sci re ceiver is double-buffered, the program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user?s program that handles receive data. refer to section 11.3.4, ?interrupts and status flags ? for more details about flag clearing. 11.3.3.1 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiv er starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is defined as a logic 0 sample after thre e consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a fa lling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure th is was a real start bit a nd not merely noise. if at least two of these three samples ar e 0, the receiver assumes it is s ynchronized to a receive character. the receiver then samples each bi t time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in th e case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including th e start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (nf) will be set wh en the received character is transferred to the receive data buffer. the falling edge detection l ogic continuously looks for fall ing edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis be cause some characters do not have any extra falling edges anywhe re in the character frame. in the case of a framing error, pr ovided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new charac ters until the framing error flag is cleared. the receive shift register continues to f unction, but a complete character cannot transfer to the receive data buffer if fe is still set. 11.3.3.2 receiver wakeup operation receiver wakeup is a hardware mech anism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu bit is set, the status flags associated with th e receiver (with the exception of the idle bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 205 message characters. at the end of a message, or at the beginning of the ne xt message, all receivers automatically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message. 11.3.3.2.1 idle-line wakeup when wake = 0, the receiver is configured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detect s a full character time of the idle-l ine level. the m control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle ar e needed to constitute a full character time (10 or 11 bit times becaus e of the start and stop bits). when rwu is one and rwuid is ze ro, the idle condition that wakes up the receiver does not set the idle flag. the receiver wakes up and waits for the first da ta character of the next message which will set the rdrf flag and generate an interrupt if enabled. wh en rwuid is one, any idle condition sets the idle flag and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit se lects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit a nd any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 11.3.3.2.2 address-mark wakeup when wake = 1, the receiver is configured for a ddress-mark wakeup. in this mode, rwu is cleared automatically when the receiver detect s a logic 1 in the most significant bi t of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wakeup allows messages to contain idle characters but re quires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf flag. in this case the ch aracter with the msb set is received even though the receiver was sleeping during most of this character time. 11.3.4 interrupts and status flags the sci system has three se parate interrupt vectors to reduce the amount of softwa re needed to isolate the cause of the interrupt. one interrupt vector is associated with th e transmitter for tdre and tc events. another interrupt vector is associ ated with the receiver for rdrf, idle, rxedgif and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separately masked by local interr upt enable masks. the flags can still be polled by software when the local masks are cleared to disable gene ration of hardware interrupt requests. the sci transmitter has two status fl ags that optionally can generate hard ware interrupt re quests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (t c) indicates that the transmitter is finished transmitting all data, preamble , and break characters and is idle with txd at the inactive level. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a ha rdware interrupt will be requested whenever tc = 1.
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 206 freescale semiconductor instead of hardware interrupts, soft ware polling may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared by reading scixs1 while rdrf = 1 and then reading scixd. when polling is used, this sequence is naturally sati sfied in the normal course of the user program. if hardware interrupts are used, scixs1 mu st be read in the interrupt servi ce routine (isr). normally, this is done in the isr anyway to check for receive erro rs, so the sequence is automatically satisfied. the idle status flag includes logic th at prevents it from ge tting set repeatedly when the rxd line remains idle for an extended period of time . idle is cleared by reading scixs1 while idle = 1 and then reading scixd. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received ch aracter that caused rdrf to be set, the error flags ? noise flag (nf), framing error (fe) , and parity error flag (pf) ? get set at the same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is rea dy to be transferred from the receive shifter to the receive data buffer, the overrun (or) flag gets set inst ead the data along with any associated nf, fe, or pf condition is lost. at any time, an active edge on th e rxd serial data input pin causes the rxedgif flag to set. the rxedgif flag is cleared by writing a ?1? to it. this function doe s depend on the receiver being enabled (re = 1). 11.3.5 additional sci functions the following sections descri be additional sci functions. 11.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be conf igured to operate in 9-bi t data mode by setting the m control bit in scixc1. in 9-bit m ode, there is a ninth data bit to th e left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scix c3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. if the bit value to be transm itted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker.
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 207 11.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci regist er data is lost and must be re-i nitialized upon reco very from these two stop modes. no sci module regi sters are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode, but not in stop2.. an active edge on the receive input brings the cpu out of stop3 mode if the interrupt is not masked (rxedgie = 1). note, because the clocks are halted, the sci module will resume operation upon ex it from stop (only in stop3 mode). software should ensure stop mode is not entered while ther e is a character being transmitted out of or received into the sci module. 11.3.5.3 loop mode when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is someti mes used to check software, independent of connections in the external system, to help isolate system pr oblems. in this mode, th e transmitter output is internally connected to the receiver input and the rx d pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 11.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). single- wire mode is used to implemen t a half-duplex serial connection. the receiver is internally connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the tx dir bit in scixc3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmit ter is temporarily disconnected from the txd pin so an external de vice can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wi re mode, the internal l oop back connection from the transmitter to the receiver causes the receiver to receive characte rs that are sent out by the transmitter.
serial communications interface (s08sciv4) mc9s08ac16 series data sheet, rev. 8 208 freescale semiconductor
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 209 chapter 12 serial peripheral interface (s08spiv3) 12.1 introduction the mc9s08ac16 series has one serial peripheral inte rface (spi) module. the four pins associated with spi functionality are shared with port e pins 4?7. see appendix a, ?electrical ch aracteristics and timing specifications ,? for spi electrical parametric information. note ignore any references to stop1 low-power mode in th is chapter, because the mc9s08ac16 series does not support it.
chapter 12 serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 210 freescale semiconductor figure 12-1. mc9s08ac16 block diagram highlighting the spi ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 211 12.1.1 features features of the spi module include: ? master or slave mode operation ? full-duplex or single-w ire bidirectional option ? programmable transmit bit rate ? double-buffered transmit and receive ? serial clock phase and polarity options ? slave select output ? selectable msb-first or lsb-first shifting 12.1.2 block diagrams this section includes block diagrams showing spi system c onnections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate. 12.1.2.1 spi system block diagram figure 12-2 shows the spi modules of two mcus connected in a master-slave ar rangement. the master device initiates all spi data transfers. during a transfer, the master sh ifts data out (on th e mosi pin) to the slave while simultaneously shifting data in (on the mi so pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input (ss pin). in this system, the mast er device has c onfigured its ss pin as an optional slave select output. figure 12-2. spi system connections 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter ss spsck miso mosi ss spsck miso mosi master slave
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 212 freescale semiconductor the most common uses of the spi system include c onnecting simple shift regi sters for adding input or output ports or connecting small pe ripheral devices such as serial a/d or d/a converters. although figure 12-2 shows a system where data is exchanged between two mcus, many practical systems involve simpler connections where data is unidirectionally transfer red from the master mcu to a slave or from a slave to the master mcu. 12.1.2.2 spi module block diagram figure 12-3 is a block diagram of the spi module. the central element of th e spi is the spi shift register. data is written to the d ouble-buffered transmitter (wri te to spi1d) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from spi1d). pin multiplexing logic controls connections between mcu pins and the spi module. when the spi is configured as a master, the clock out put is routed to the spsc k pin, the shifter output is routed to mosi, and the shifter i nput is routed from the miso pin. when the spi is configured as a slave, the spsck pin is routed to the clock i nput of the spi, the shifter output is routed to miso, and the shifte r input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly di fferent names for these pins.
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 213 figure 12-3. spi module block diagram 12.1.3 spi baud rate generation as shown in figure 12-4 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) di vide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie modfen ssoe spc0 bidiroe spibr tx buffer (write spi1d) rx buffer (read spi1d)
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 214 freescale semiconductor figure 12-4. spi baud rate generation 12.2 external signal description the spi optionally shares four port pi ns. the function of these pins depe nds on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins re vert to being general-pur pose port i/o pins that are not controlled by the spi. 12.2.1 spsck ? spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. wh en the spi is enabled as a master, this pin is the serial clock output. 12.2.2 mosi ? master data out, slave data in when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc 0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master m ode is selected, this pin becomes the bidirectional data i/o pin (mom i). also, the bidirecti onal mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a gene ral-purpose port i/o pin. 12.2.3 miso ? master da ta in, slave data out when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enable d as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is se lected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bid iroe = 1). if spc0 = 1 and ma ster mode is selected, this pin is not used by the spi and reve rts to being a general-purpose port i/o pin. 12.2.4 ss ? slave select when the spi is enabled as a slave, this pin is the lo w-true slave select input. wh en the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not us ed by the spi and reverts to being a general-purpose port i/o pin. when the spi is enab led as a master and modf en = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler clock rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 215 12.3 modes of operation 12.3.1 spi in stop modes the spi is disabled in all stop mode s, regardless of the settings befo re executing the stop instruction. during either stop1 or stop2 mode, th e spi module will be fully powered down. upon wake-up from stop1 or stop2 mode, the spi module will be in the reset st ate. during stop3 mode, cloc ks to the spi module are halted. no registers are affected. if st op3 is exited with a reset, the spi wi ll be put into its reset state. if stop3 is exited with an interrupt, the spi continues from the state it was in when stop3 was entered. 12.4 register definition the spi has five 8-bit registers to select spi options, control ba ud rate, report spi status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all spi registers. this section refers to register s and control bits only by their names, and a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.4.1 spi control register 1 (spi1c1) this read/write register includes the spi enable control, interrupt enables, and configuration options. 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset00000100 figure 12-5. spi control register 1 (spi1c1) table 12-1. spi1c1 field descriptions field description 7 spie spi interrupt enable (for sprf and modf) ? this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 0 interrupts from sprf and modf inhibited (use polling) 1 when sprf or modf is 1, request a hardware interrupt 6 spe spi system enable ? disabling the spi halts any trans fer that is in progress, clears data buffers, and initializes internal state machines. sprf is cleared and sptef is set to indicate the spi transmit data buffer is empty. 0 spi system inactive 1 spi system enabled 5 sptie spi transmit interrupt enable ? this is the interrupt enable bit for spi transmit buffer empty (sptef). 0 interrupts from sptef inhibited (use polling) 1 when sptef is 1, hardware interrupt requested
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 216 freescale semiconductor note ensure that the spi should not be disa bled (spe=0) at the same time as a bit change to the cpha bit. these changes should be performed as separate operations or unexpected behavior may occur. 12.4.2 spi control register 2 (spi1c2) this read/write register is used to control optional featur es of the spi system. bits 7, 6, 5, and 2 are not implemented and always read 0. 4 mstr master/slave mode select 0 spi module configured as a slave spi device 1 spi module configured as a master spi device 3 cpol clock polarity ? this bit effectively places an inverter in seri es with the clock signal from a master spi or to a slave spi device. refer to section 12.5.1, ?spi clock formats ? for more details. 0 active-high spi clock (idles low) 1 active-low spi clock (idles high) 2 cpha clock phase ? this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to section 12.5.1, ?spi clock formats ? for more details. 0 first edge on spsck occurs at the middle of the first cycle of an 8-cycle data transfer 1 first edge on spsck occurs at the start of the first cycle of an 8-cycle data transfer 1 ssoe slave select output enable ? this bit is used in combination with the mode fault enable (modfen) bit in spcr2 and the master/slave (mstr) contro l bit to determine the function of the ss pin as shown in table 12-2 . 0 lsbfe lsb first (shifter direction) 0 spi serial data transfers start with most significant bit 1 spi serial data transfers start with least significant bit table 12-2. ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10ss input for mode fault slave select input 1 1 automatic ss output slave select input 76543210 r000 modfen bidiroe 0 spiswai spc0 w reset00000000 = unimplemented or reserved figure 12-6. spi control register 2 (spi1c2) table 12-1. spi1c1 field descriptions (continued) field description
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 217 12.4.3 spi baud rate register (spi1br) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. table 12-3. spi1c2 register field descriptions field description 4 modfen master mode-fault function enable ? when the spi is configured for sl ave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in mast er mode, this bit determines how the ss pin is used (refer to ta b l e 1 2 - 2 for more details). 0 mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi 1 mode fault function enabled, master ss pin acts as the mode fault input or the slave select output 3 bidiroe bidirectional mode output enable ? when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is configured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/ o pin. when spc0 = 0, bidiroe has no meaning or effect. 0 output driver disabled so spi data i/o pin acts as an input 1 spi i/o pin enabled as an output 1 spiswai spi stop in wait mode 0 spi clocks continue to operate in wait mode 1 spi clocks stop when the mcu enters wait mode 0 spc0 spi pin control 0 ? the spc0 bit chooses single-wire bidirectional mode. if mstr = 0 (slave mode), the spi uses the miso (siso) pin for bidirectional spi data tr ansfers. if mstr = 1 (master mode), the spi uses the mosi (momi) pin for bidirectional spi data transfers. when spc0 = 1, bidiroe is used to enable or disable the output driver for the single bidirectional spi i/o pin. 0 spi uses separate pins for data input and data output 1 spi configured for single-wire bidirectional operation 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset00000000 = unimplemented or reserved figure 12-7. spi baud rate register (spi1br) table 12-4. spi1br register field descriptions field description 6:4 sppr[2:0] spi baud rate prescale divisor ? this 3-bit field selects one of eight divisors for the spi baud rate prescaler as shown in ta b l e 1 2 - 5 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 12-4 ). 2:0 spr[2:0] spi baud rate divisor ? this 3-bit field selects one of eight diviso rs for the spi baud rate divider as shown in ta b l e 1 2 - 6 . the input to this divider comes from the spi baud rate prescaler (see figure 12-4 ). the output of this divider is the spi bit rate clock for master mode.
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 218 freescale semiconductor 12.4.4 spi status register (spi1s) this register has three read-only st atus bits. bits 6, 3, 2, 1, and 0 are not implemented and always read 0. writes have no meaning or effect. table 12-5. spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 table 12-6. spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 76543210 r sprf 0 sptef modf 0 0 0 0 w reset00100000 = unimplemented or reserved figure 12-8. spi status register (spi1s)
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 219 12.4.5 spi data register (spi1d) reads of this register return the data read from the rece ive data buffer. writes to th is register write data to the transmit data buffer. when the spi is configured as a master, writi ng data to the transmit data buffer initiates an spi transfer. data should not be written to the transmit data buf fer unless the spi transmit buffer empty flag (sptef) is set, indicating there is room in the tr ansmit buffer to queue a new transmit byte. data may be read from spi1d any ti me after sprf is set and before anot her transfer is finished. failure to read the data out of the receive data buffer before a new transfer ends causes a recei ve overrun condition and the data from the new transfer is lost. table 12-7. spi1s register field descriptions field description 7 sprf spi read buffer full flag ? sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spi 1d). sprf is cleared by reading sprf while it is set, then reading the spi data register. 0 no data available in the receive data buffer 1 data available in the receive data buffer 5 sptef spi transmit buffer empty flag ? this bit is set when there is room in the transmit data buffer. it is cleared by reading spi1s with sptef set, followed by writing a data value to the transmit buffer at spi1d. spi1s must be read with sptef = 1 before writing data to spi1d or the spi1d write will be igno red. sptef generates an sptef cpu interrupt request if the sptie bit in the spi1 c1 is also set. sptef is automatically set when a data byte transfers from the transmit buffer into the transmit shi ft register. for an idle spi (no data in the transmit buffer or the shift register and no transfer in progress), data written to spi1d is transferred to the shifter almost immediately so sptef is set within two bus cycles allowing a second 8-bi t data value to be queued into the transmit buffer. after completion of the transfer of the va lue in the shift register, the queued value from the transmit buffer will automatically move to the shifter and sptef wi ll be set to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer, sptef simply remains set and no data moves from the buffer to the shifter. 0 spi transmit buffer not empty 1 spi transmit buffer empty 4 modf master mode fault flag ? modf is set if the spi is configured as a master and the slave select input goes low, indicating some other spi device is also configured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spi1c1). 0 no mode fault error 1 mode fault error detected 76543210 r bit 7654321bit 0 w reset00000000 figure 12-9. spi data register (spi1d)
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 220 freescale semiconductor 12.5 functional description an spi transfer is initiated by checking for the spi transmit buffer empty flag (sptef = 1) and then writing a byte of data to the spi data register (spi1d) in the master spi device. when the spi shift register is available, this byte of data is m oved from the transmit data buffer to th e shifter, sptef is set to indicate there is room in the buffer to queue another transmit character if desired, and the spi serial transfer starts. during the spi transfer, data is sampled (read) on th e miso pin at one spsck e dge and shifted, changing the bit value on the mosi pin, one-half spsck cycle la ter. after eight spsck cycles, the data that was in the shift register of the master has been shifted out the mosi pin to the slave while eight bits of data were shifted in the miso pin into the master?s shift re gister. at the end of this transfer, the received data byte is moved from the shifter into th e receive data buffer and sprf is set to indicate the da ta can be read by reading spi1d. if another byte of da ta is waiting in the transmit buffe r at the end of a transfer, it is moved into the shifter, sptef is se t, and a new transfer is started. normally, spi data is transferred most significant bit (msb) first. if th e least significant bit first enable (lsbfe) bit is set, spi data is shifted lsb first. when the spi is configur ed as a slave, its ss pin must be driven low befo re a transfer starts and ss must stay low throughout the tran sfer. if a clock format wh ere cpha = 0 is selected, ss must be driven to a logic 1 between successive transfers. if cpha = 1, ss may remain low between successive transfers. see section 12.5.1, ?spi clock formats ? for more details. because the transmitter a nd receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffe r, and a previously rece ived character can be in the receive data buffer while a new character is being shifted in. the sptef flag indicates when the transmit buffer has room for a new character. the sprf flag indicates when a received character is available in the receive data buffer. the received char acter must be read out of the receive buffer (read spi1d) before the next transfer is fini shed or a receive overrun error results. in the case of a receive overrun, the new data is lo st because the receive buffer still held the previous character and was not ready to accept the new data. there is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 12.5.1 spi clock formats to accommodate a wide variety of synchronous serial peripherals from differen t manufacturers, the spi system has a clock polarity (cpol) bi t and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol se lectively inserts an inverter in se ries with the clock. cpha chooses between two different clock phase rela tionships between the clock and data. figure 12-10 shows the clock formats when cpha = 1. at th e top of the figure, th e eight bit times are shown for reference with bit 1 st arting at the first spsck edge a nd bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb first and ls b first lines show the or der of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are show n, but only one of these waveforms applies for a specific transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slav e or the miso input of a master. the mosi waveform applies to the
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 221 mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output fr om a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle befo re the start of the transfer and goes back high at the end of the eighth bi t time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 12-10. spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not defined until the first spsck edge. the first spsck edge shifts the first bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi input s, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when chpa = 1, the slave?s ss input is not required to go to its inactive high level between transfers. figure 12-11 shows the clock formats when cpha = 0. at th e top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (ss in goes low), and bit 8 ends at the last spsck edge. the msb first and lsb fi rst lines show the order of spi data bits dependi ng on the setting bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 222 freescale semiconductor in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the va lue in cpol. the sample in wave form applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso wavefo rm applies to the miso out put from a slave. the ss out waveform applies to the slave select output fr om a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the fi rst bit time of the transfer and goe s back high one-half spsck cycle after the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 12-11. spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the first data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the first spsck edge causes both the master and the slave to sample the data bit valu es on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was ju st sampled and shifts the second data bit value out the other end of the shifte r to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slave?s ss input must go to its in active high level between transfers. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 223 12.5.2 spi interrupts there are three flag bits, two interr upt mask bits, and one interrupt vect or associated with the spi system. the spi interrupt enable mask (spie) enables interrupt s from the spi receiver full flag (sprf) and mode fault flag (modf). the spi transm it interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty fl ag (sptef). when one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated flag bits instead of using inte rrupts. the spi interrupt se rvice routine (isr) should check the flag bits to de termine what event caused the interrupt. the service routine s hould also clear the flag bit(s) before returning from the is r (usually near the beginning of the isr). 12.5.3 mode fault detection a mode fault occurs and th e mode fault flag (modf) becomes set wh en a master spi device detects an error on the ss pin (provided the ss pin is configured as the m ode fault input signal). the ss pin is configured to be the mode fault input signal when mstr = 1, mode fault enable is set (modfen = 1), and slave select output enable is clear (ssoe = 0). the mode fault detection f eature can be used in a system where mo re than one spi de vice might become a master at the same t ime. the error is detect ed when a master?s ss pin is low, indicating that some other spi device is trying to addre ss this master as if it were a slave. th is could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all spi output driver s when such an error is detected. when a mode fault is detected, modf is set and mstr is cleared to change the spi configuration back to slave mode. the output drivers on the spsck, mo si, and miso (if not bi directional mode) are disabled. modf is cleared by reading it while it is set, then writing to the spi control register 1 (spi1c1). user software should verify the error c ondition has been corrected before changing the spi back to master mode.
serial peripheral interface (s08spiv3) mc9s08ac16 series data sheet, rev. 8 224 freescale semiconductor
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 225 chapter 13 inter-integrated circuit (s08iicv2) 13.1 introduction the mc9s08ac16 series series of microcontrollers has an inter-inte grated circuit (iic) module for communication with other inte grated circuits. the two pins associat ed with this module, scl and sda, are shared with port c pins 0 and 1, respectively. note ignore any references to stop1 low-power mode in th is chapter, because the mc9s08ac16 series does not support it.
chapter 13 inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 226 freescale semiconductor figure 13-1. mc9s08ac16 block diagram highlighting the iic ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 227 13.1.1 features the iic includes these distinctive features: ? compatible with iic bus standard ? multi-master operation ? software programmable for one of 64 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection ? general call recognition ? 10-bit address extension 13.1.2 modes of operation a brief description of the iic in th e various mcu modes is given here. ? run mode ? this is the basic mode of operation. to conserve power in th is mode, disable the module. ? wait mode ? the module continues to operate while th e mcu is in wait mode and can provide a wake-up interrupt. ? stop mode ? the iic is inactive in stop3 mode fo r reduced power consumption. the stop instruction does not affect iic register st ates. stop2 resets the register contents. 13.1.3 block diagram figure 13-2 is a block diagram of the iic.
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 228 freescale semiconductor figure 13-2. iic functional block diagram 13.2 external signal description this section describes each user-accessible pin signal. 13.2.1 scl ? serial clock line the bidirectional scl is the serial clock line of the iic system. 13.2.2 sda ? serial data line the bidirectional sda is the serial data line of the iic system. 13.3 register definition this section consists of the iic regi ster descriptions in address order. refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 229 freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 iic address register (iic1a) 13.3.2 iic frequency divider register (iic1f) 76543210 r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w reset00000000 = unimplemented or reserved figure 13-3. iic address register (iic1a) table 13-1. iic1a field descriptions field description 7?1 ad[7:1] slave address. the ad[7:1] field contains the slave address to be used by the iic module. this field is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 76543210 r mult icr w reset00000000 figure 13-4. iic frequency divider register (iic1f)
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 230 freescale semiconductor for example, if the bus speed is 8 m hz, the table below shows the possibl e hold time values with different icr and mult selections to achie ve an iic baud rate of 100kbps. table 13-2. iic1f field descriptions field description 7?6 mult iic multiplier factor . the mult bits define the multiplier factor, mu l. this factor, along with the scl divider, generates the iic baud rate. the multiplier factor mu l as defined by the mult bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 reserved 5?0 icr iic clock rate . the icr bits are used to prescale the bus clock for bit rate selection. these bits and the mult bits determine the iic baud rate, the sda hold time, the scl start hold time, and the scl stop hold time. ta b l e 1 3 - 4 provides the scl divider and hold values for corresponding values of the icr. the scl divider multiplied by multiplier factor mul generates iic baud rate. eqn. 13-1 sda hold time is the delay from the falling edge of scl (iic clock) to the changing of sda (iic data). sda hold time = bus period (s) mul sda hold value eqn. 13-2 scl start hold time is the delay from the falling edge of sda (iic data) while scl is high (start condition) to the falling edge of scl (iic clock). scl start hold time = bus period (s) mul scl start hold value eqn. 13-3 scl stop hold time is the delay from the rising edge of scl (iic clock) to the rising edge of sda sda (iic data) while scl is high (stop condition). scl stop hold time = bus period (s) mul scl stop hold value eqn. 13-4 table 13-3. hold time values for 8 mhz bus speed mult icr hold times ( s) sda scl start scl stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0b 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 iic baud rate bus speed (hz) mul scldivider -------------------------------------------- - =
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 231 table 13-4. iic divider and hold values icr (hex) scl divider sda hold value scl hold (start) value sda hold (stop) value icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0a 36 9 14 19 2a 448 65 222 225 0b 40 9 16 21 2b 512 65 254 257 0c 44 11 18 23 2c 576 97 286 289 0d 48 11 20 25 2d 640 97 318 321 0e 56 13 24 29 2e 768 129 382 385 0f 68 13 30 35 2f 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1a 112 17 54 57 3a 1792 257 894 897 1b 128 17 62 65 3b 2048 257 1022 1025 1c 144 25 70 73 3c 2304 385 1150 1153 1d 160 25 78 81 3d 2560 385 1278 1281 1e 192 33 94 97 3e 3072 513 1534 1537 1f 240 33 118 121 3f 3840 513 1918 1921
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 232 freescale semiconductor 13.3.3 iic control register (iic1c1) 13.3.4 iic status register (iic1s) 76543210 r iicen iicie mst tx txak 000 w rsta reset00000000 = unimplemented or reserved figure 13-5. iic control register (iic1c1) table 13-5. iic1c1 field descriptions field description 7 iicen iic enable. the iicen bit determines whether the iic module is enabled. 0 iic is not enabled 1 iic is enabled 6 iicie iic interrupt enable. the iicie bit determines whether an iic interrupt is requested. 0 iic interrupt request not enabled 1 iic interrupt request enabled 5 mst master mode select. the mst bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0slave mode 1 master mode 4 tx transmit mode select. the tx bit selects the direction of master and slave transfers. in master mode, this bit should be set according to the type of transfer required. therefore, for address cycles, this bit is always high. when addressed as a slave, this bit should be set by software according to the srw bit in the status register. 0 receive 1 transmit 3 txak transmit acknowledge enable. this bit specifies the value driven onto the sda during data acknowledge cycles for master and slave receivers. 0 an acknowledge signal is sent out to the bus after receiving one data byte 1 no acknowledge signal response is sent 2 rsta repeat start. writing a 1 to this bit generates a repeated start condition provided it is the current master. this bit is always read as cleared. attempting a repeat at the wrong time results in loss of arbitration. 76543210 rtcf iaas busy arbl 0srw iicif rxak w reset10000000 = unimplemented or reserved figure 13-6. iic status register (iic1s)
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 233 13.3.5 iic data i/o register (iic1d) table 13-6. iic1s field descriptions field description 7 tcf transfer complete flag. this bit is set on the completion of a byte transfer. this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iic1d register in receive mode or writing to the iic1d in transmit mode. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave. the iaas bit is set when the calling address matches the programmed slave address or when the gcaen bit is set and a general call is re ceived. writing the iic1c register clears this bit. 0 not addressed 1 addressed as a slave 5 busy bus busy. the busy bit indicates the status of the bus regardl ess of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 0 bus is idle 1bus is busy 4 arbl arbitration lost. this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software by writing a 1 to it. 0 standard bus operation 1 loss of arbitration 2 srw slave read/write. when addressed as a slave, the srw bit indica tes the value of the r/w command bit of the calling address sent to the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 iicif iic interrupt flag. the iicif bit is set when an interrupt is pendi ng. this bit must be cleared by software, by writing a 1 to it in the interrupt routine. o ne of the following events can set the iicif bit: ? one byte transfer completes ? match of slave address to calling address ? arbitration lost 0 no interrupt pending 1 interrupt pending 0 rxak receive acknowledge . when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 0 acknowledge received 1 no acknowledge received 76543210 r data w reset00000000 figure 13-7. iic data i/o register (iic1d)
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 234 freescale semiconductor note when transitioning out of master r eceive mode, the iic mode should be switched before reading the iic1d re gister to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are avai lable after an addres s match has occurred. the tx bit in iic1c must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is c onfigured for master transmit but a master receive is desired, reading the iic1d doe s not initiate the receive. reading the iic1d returns the last byte received while the ii c is configured in master receive or slave receive modes. the iic1d does not reflect every byte tr ansmitted on the iic bus, nor can software verify that a byte has been written to the iic1d correctly by reading it back. in master transmit mode, th e first byte of data written to iic1d foll owing assertion of ms t is used for the address transfer and should comprise of the calling addr ess (in bit 7 to bit 1) conc atenated with the required r/w bit (in position bit 0). 13.3.6 iic control register 2 (iic1c2) table 13-7. iic1d field descriptions field description 7?0 data data ? in master transmit mode, when data is written to the iic1d, a data transfer is initiated. the most significant bit is sent first. in master receive mode, reading th is register initiates receiving of the next byte of data. 76543210 r gcaen adext 000 ad10 ad9 ad8 w reset00000000 = unimplemented or reserved figure 13-8. iic control register (iic1c2) table 13-8. iic1c2 field descriptions field description 7 gcaen general call address enable. the gcaen bit enables or disables general call address. 0 general call address is disabled 1 general call address is enabled 6 adext address extension. the adext bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2?0 ad[10:8] slave address. the ad[10:8] field contains the upper three bits of the slave address in the 10-bit address scheme. this field is only valid when the adext bit is set.
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 235 13.4 functional description this section provides a complete func tional description of the iic module. 13.4.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for da ta transfer. all devices connected to it must have open drain or open collec tor outputs. a logic and function is exercised on both lines with external pull-up resistors. the va lue of these resistors is system dependent. normally, a standard communication is composed of four parts: ? start signal ? slave address transmission ? data transfer ? stop signal the stop signal should not be confus ed with the cpu stop instruction. the iic bus system communication is described briefly in the follow ing sections and illustrated in figure 13-9 . figure 13-9. iic bus transmission signals 13.4.1.1 start signal when the bus is free, no master de vice is engaging the bus (scl and sda lines are at logical high), a master may initiate communication by se nding a start signal. as shown in figure 13-9 , a start signal is defined as a high-to-low transition of sda while scl is high. this si gnal denotes the beginning of a new data transfer (each data transfer ma y contain several bytes of data) and br ings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 12 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 236 freescale semiconductor 13.4.1.2 slave address transmission the first byte of data transferred im mediately after the start signal is th e slave address transmitted by the master. this is a seven-bit ca lling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling addr ess that matches the one transmitt ed by the master responds by sending back an acknowledge bit. this is done by pul ling the sda low at the ninth clock (see figure 13-9 ). no two slaves in the system may have the same a ddress. if the iic module is the master, it must not transmit an address equal to its ow n slave address. the iic cannot be ma ster and slave at the same time. however, if arbitration is lost duri ng an address cycle, the iic reverts to slave mode and operates correctly even if it is being a ddressed by another master. 13.4.1.3 data transfer before successful slave addressing is achieved, the da ta transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 13-9 . there is one clock pulse on scl fo r each data bit, the msb being transferred first. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at th e ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowledge the master in the ninth bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsu ccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is abor ted and the master does one of two things: ? relinquishes the bus by generating a stop signal. ? commences a new calling by gene rating a repeated start signal. 13.4.1.4 stop signal the master can terminate the comm unication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a ca lling command without gene rating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-h igh transition of sda while scl at logical 1 (see figure 13-9 ). the master can generate a stop even if the slave ha s generated an acknowledge at which point the slave must release the bus.
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 237 13.4.1.5 repeated start signal as shown in figure 13-9 , a repeated start signal is a start signal generated wi thout first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (tra nsmit/receive mode) wit hout releasing the bus. 13.4.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a cl ock synchronization proce dure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the re lative priority of the c ontending masters is determin ed by a data arbitration procedure, a bus master lose s arbitration if it transm its logic 1 while another ma ster transmits logic 0. the losing masters immediately switch ove r to slave receive mode and stop driving sda output. in this case, the transition from master to slave mode does not ge nerate a stop condition. meanwh ile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. th e devices start counting their low pe riod and after a device?s clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 13-10 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again. figure 13-10. iic clock synchronization scl1 scl2 scl internal counter reset delay start counting high period
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 238 freescale semiconductor 13.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byt e transfer (9 bits). in such a ca se, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 13.4.1.9 clock stretching the clock synchronization mechanism ca n be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive sc l low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 13.4.2 10-bit address for 10-bit addressing, 0x11110 is used fo r the first 5 bits of the first addr ess byte. various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 13.4.2.1 master-transmitter addresses a slave-receiver the transfer direction is not changed (see table 13-9 ). when a 10-bit address follows a start condition, each slave compares the first seven bits of the fi rst byte of the slave address (11110xx) with its own address and tests whet her the eighth bit (r/w direction bit) is 0. more th an one device can find a match and generate an acknowledge (a1). then, each slave that finds a matc h compares the eight bits of the second byte of the slave a ddress with its own addre ss. only one slave finds a match and generates an acknowledge (a2). the matchi ng slave remains addressed by the mast er until it recei ves a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an iic interrupt. software must ensure the contents of iicd are i gnored and not treated as valid data for this interrupt. 13.4.2.2 master-receiver addr esses a slave-transmitter the transfer direction is changed after the second r/w bit (see table 13-10 ). up to and including acknowledge bit a2, the pro cedure is the same as th at described for a master-transmitter addressing a slave-receiver. after the repeated start condition (sr), a matching slav e remembers that it was addressed before. this slave then checks whether the first seven bits of the first byte of the slave address following sr are the same as they were after the start condition (s) a nd tests whether the eighth (r/w ) bit is 1. if there is a match, the slave considers that it has been addresse d as a transmitter and generates acknowledge a3. the slave-transmitter remains addres sed until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 data a ... data a/a p 11110 + ad10 + ad9 0 ad[8:1] table 13-9. master-transmitter addresses slave-receiver with a 10-bit address
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 239 after a repeated start condition (sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (r/w ) bit. however, none of them are addressed because r/w = 1 (for 10-bit devices) or the 11110xx slave address (for 7-bit devices) does not match. after the master-receiver has sent the first byte of th e 10-bit address, the slav e-transmitter sees an iic interrupt. software must ensure the contents of iicd are i gnored and not treated as valid data for this interrupt. 13.4.3 general call address general calls can be requested in 7- bit address or 10-bit addr ess. if the gcaen bit is set, the iic matches the general call address as well as its own slave addres s. when the iic responds to a general call, it acts as a slave-receiver and the iaas bit is set after the address cycl e. software must read the iicd register after the first byte transfer to determine whether the address matche s is its own slave addr ess or a general call. if the value is 00, the match is a ge neral call. if the gcaen bit is clear , the iic ignores any data supplied from a general call address by not issuing an acknowledgement. 13.5 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 13.6 interrupts the iic generates a single interrupt. an interrupt from the iic is gene rated when any of the events in table 13-11 occur, provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by softwa re by writing a 1 to it in the interrupt routine. you can determine the interrupt type by reading the status register. 13.6.1 byte transfer interrupt the tcf (transfer complete flag) bit is set at the falling edge of the ni nth clock to indica te the completion of byte transfer. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 sr slave address 1st 7 bits r/w a3 data a ... data a p 11110 + ad10 + ad9 0 ad[8:1] 11110 + ad10 + ad9 1 table 13-10. master-receiver addresses a slave-transmitter with a 10-bit address table 13-11. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 240 freescale semiconductor 13.6.2 address detect interrupt when the calling address matches the programmed slav e address (iic address register) or when the gcaen bit is set and a general call is received, the ia as bit in the status register is set. the cpu is interrupted, provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. 13.6.3 arbitration lost interrupt the iic is a true mul ti-master bus that allo ws more than one mast er to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of th e contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt wh en it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in th e following circumstances: ? sda sampled as a low when the master drives a high during an address or data transmit cycle. ? sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. this bit must be cleared by software writing a 1 to it.
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 241 13.7 initialization/application information figure 13-11. iic module quick start module initialization (slave) 1. write: iicc2 ? to enable or disable general call ? to select 10-bit or 7-bit addressing mode 2. write: iica ? to set the slave address 3. write: iicc1 ? to enable iic and interrupts 4. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 5. initialize ram variables used to achieve the routine shown in figure 13-12 module initialization (master) 1. write: iicf ? to set the iic baud rate (examp le provided in this chapter) 2. write: iicc1 ? to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 13-12 5. write: iicc1 ? to enable tx 0 iicf iica baud rate = busclk / (2 x mult x (scl divider)) tx txak rsta 0 0 iicc1 iicen iicie mst module configuration arbl 0 srw iicif rxak iics tcf iaas busy module status flags register model ad[7:1] when addressed as a slave (in slave mode), the module responds to this address mult icr iicd data data register; write to transmit iic data read to read iic data 0 ad10 ad9 ad8 iicc2 gcaen adext address configuration 0 0
inter-integrated circuit (s08iicv2) mc9s08ac16 series data sheet, rev. 8 242 freescale semiconductor figure 13-12. typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to iicd switch to rx mode dummy read from iicd generate stop signal read data from iicd and store set txack =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear arbl iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to iicd set rx mode dummy read from iicd ack from receiver ? tx next byte read data from iicd and store switch to rx mode dummy read from iicd rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iicif address transfer data transfer (mst = 0) (mst = 0) see note 1 notes: 1. if general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). if the received address was a general call address, then the general call must be handled by user software. 2. when 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address . user software must ensure that for this interrupt, the contents of iicd are ignored and not treated as a valid data transfer. see note 2
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 243 chapter 14 analog-to-digital converter (s08adc10v1) 14.1 overview the 10-bit analog-to-digital convert er (adc) is a successive appr oximation adc desi gned for operation within an integrated microcontroller system-on-ch ip. the adc module design supports up to 28 separate analog inputs (ad0-ad27). only 9 (ad0-ad3, ad8-ad11, and ad27) of the possible inputs are implemented on the mc9s08ac16 series family of mc us. these inputs are selected by the adch bits. some inputs are shared with i/o pins as shown in figure 14-1 . all of the channel a ssignments of the adc for the mc9s08ac16 series devices are summarized in table 14-1 . note ignore any references to stop1 low-power mode in th is chapter, because the mc9s08ac16 series does not support it. 14.2 channel assignments the adc channel assignments for the mc9s08ac16 se ries devices are shown in the table below. channels that are unimplemented are internally connected to v refl . reserved channels convert to an unknown value. channels which are connected to an i/o pin ha ve an associated pin control bit as shown. table 14-1. adc channel assignment adch channel input pin control adch channel input pin control 00000 ad0 ptb0/ad1p0 adpc0 10000 ad16 v refl n/a 00001 ad1 ptb1/ad1p1 adpc1 10001 ad17 v refl n/a 00010 ad2 ptb2/ad1p2 adpc2 10010 ad18 v refl n/a 00011 ad3 ptb3/ad1p3 adpc3 10011 ad19 v refl n/a 00100 ad4 v refl n/a 10100 ad20 v refl n/a 00101 ad5 v refl n/a 10101 ad21 v refl n/a 00110 ad6 v refl n/a 10110 ad22 reserved n/a 00111 ad7 v refl n/a 10111 ad23 reserved n/a 01000 ad8 ptd0/ad1p8 adpc8 11000 ad24 reserved n/a 01001 ad9 ptd1/ad1p9 adpc9 11001 ad25 reserved n/a 01010 ad10 ptd2/ad1p10 adpc10 11010 ad26 temp sensor n/a 01011 ad11 ptd3/ad1p11 adpc11 11011 ad27 internal bandgap n/a 01100 ad12 v refl n/a 11100 reserved n/a 01101 ad13 v refl n/a 11101 v refh v refh n/a 01110 ad14 v refl n/a 11110 v refl v refl n/a
chapter 14 analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 244 freescale semiconductor note selecting the internal bandgap channe l requires bgbe =1 in spmsc1 see section 5.9.8, ?system power management status and control 1 register (spmsc1) .? for value of bandgap voltage reference see section a.6, ?dc characteristics .? 14.2.1 alternate clock the adc module is capable of perf orming conversions using the mcu bus clock, the bus clock divided by two, the local asynchronous clock (adack) within the module, or the alte rnate clock, altclk. the alternate clock for the mc 9s08ac16 series mcu devices is the ex ternal reference clock (icgerclk) from the internal cloc k generator (icg) module. because icgerclk is active only whil e an external clock source is enab led, the icg must be configured for either fbe or fee mode (clks1 = 1). icgercl k must run at a frequency such that the adc conversion clock (adck) runs at a fr equency within its specified range (f adck ) after being divided down from the altclk input as determined by the adiv bits. for example, if the adiv bits are set up to divide by four, then the minimum frequency for altclk (i cgerclk) is four times the minimum value for f adck and the maximum frequency is f our times the maximum value for f adck . because of the minimum frequency requirement, when an osci llator circuit is used it must be configured for high range operation (range = 1). altclk is active while the mcu is in wait mode provided the conditi ons described above are met. this allows altclk to be used as the conversion clock source for the adc while the mcu is in wait mode. altclk cannot be used as the adc conversi on clock source while the mcu is in stop3. 14.2.2 hardware trigger the adc hardware trigger, adhwt, is output from the real time inte rrupt (rti) counter. the rti counter can be clocked by either icgerclk or a nominal 1 khz cl ock source within the rti block. the 1-khz clock source can be used with the mcu in run, wait, or stop3. with the icg config ured for either fbe or fee mode, icgerclk can be used with the mcu in run or wait. the period of the rti is determined by the input clock frequency and the rtis bits. when the adc hardware trigger is enabled, a conversion is initiate d upon an rti counter overflow. the rti counter is a free running counter that generates an overflow at the rti rate determined by the rtis bits. 14.2.2.1 analog pin enables the adc on mc9s08ac16 series cont ains only two analog pin enable registers, apctl1 and apctl2. 01111 ad15 v refl n/a 11111 module disabled none n/a table 14-1. adc channel assignment (continued) adch channel input pin control adch channel input pin control
chapter 14 analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 245 14.2.2.2 low-power mode operation the adc is capable of running in stop3 mode but requires lvdse a nd lvde in spmsc1 to be set. 14.2.3 temperature sensor the adc1 module includes a temperature sensor whos e output is connected to one of the adc analog channel inputs. equation 14-1 provides an approximate transfer function of the te mperature sensor. temp = 25 - ((v temp -v temp25 ) m) eqn. 14-1 where: ?v temp is the voltage of the temperature sens or channel at the ambient temperature. ?v temp25 is the voltage of the temperature sensor channel at 25 c. ? m is the hot or cold voltage versus temperature slope in v/ c. for temperature calculations, use the v temp25 and m values from the adc electricals table. in application code, the us er reads the temperature se nsor channel, calculates v temp , and compares to v temp25 . if v temp is greater than v temp25 the cold slope value is applied in equation 14-1 . if v temp is less than v temp25 the hot slope value is applied in equation 14-1 . to improve accuracy , calibra te the bandgap voltage refere nce and temperature sensor. calibrating at 25 c will improve accuracy to 4.5 c. calibration at 3 points, -40 c, 25 c, and 125 c will improve accuracy to 2.5 c. once calibration has been completed, the user will need to calculate the slope for both hot and cold. in application code, the user would then calculat e the temperature using equation 14-1 as detailed above and then determine if the temperature is above or below 25 c. once determined if the te mperature is above or below 25 c, the user can recalculate the temperature using the hot or cold slope va lue obtained during calibration. for more information on using the temperature sensor, consult an3031.
chapter 14 analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 246 freescale semiconductor figure 14-1. mc9s08ac16 block diagram highlighting the adc ad1p11?ad1p8 ptd3/kbip6/ad1p11 ptc1/sda1 ptc0/scl1 v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta7 pte0/txd1 pte1/rxd1 ptd2/kbip5/ad1p10 ptd1/ad1p9 ptd0/ad1p8 ptc5/rxd2 ptc4 ptc3/txd2 ptc2/mclk port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic1) serial peripheral interface module (spi1) user flash user ram debug module (dbg) 16,384 bytes hcs08 core cpu bdc notes : 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. ptd3, ptd2, and ptg4 contain both pullup and pul ldown devices. pulldown enabled when kbi is enabled (kbipen = 1) and rising edge is selected (kbedgn = 1). 2-channel timer/pwm module (tpm2) ptb3/ad1p3 port b pte5/miso1 pte4/ss1 pte6/mosi1 pte7/spsck1 hcs08 system control reset s and interrupts modes of operation power management voltage regulator rti cop irq lvd reset v ssad v ddad v refh analog-to-digital converter (adc1) 4-channel timer/pwm module (tpm1) ptb2/ad1p2 ptg4/kbip4 ptg2/kbip2 ptg3/kbip3 port g 1024 bytes 10-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg5/xtal ptg6/extal irq/tpmclk rxd2 txd2 sda1 scl1 4 ad1p3?ad1p0 kbip4?kbip0 kbip6?kbip5 tpm2ch1 spsck1 ss1 miso1 mosi1 tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 4 5 2 pta2 pta1 pta0 ptb1/tpm3ch1/ad1p1 ptb0/tpm3ch0/ad1p0 tpm2ch0 = not available on 32-, 42-, or 44-pin packages = not available on 32- or 42-pin packages = not available on 32-pin packages tpm1ch3 tpm1ch2 2-channel timer/pwm module (tpm3) tpm3ch1 tpm3ch0 tpmclk low-power oscillator internal clock generator (icg) or 8192 bytes or 768 bytes
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 247 14.2.4 features features of the adc module include: ? linear successive approximation al gorithm with 10 bits resolution. ? up to 28 analog inputs. ? output formatted in 10- or 8-bit right-justified format. ? single or continuous conversion (automatic return to idle afte r single conversion). ? configurable sample time and conversion speed/power. ? conversion complete flag and interrupt. ? input clock selectable fr om up to four sources. ? operation in wait or stop3 m odes for lower noise operation. ? asynchronous clock source for lower noise operation. ? selectable asynchronous hardware conversion trigger. ? automatic compare with interrupt for less-than, or gr eater-than or equal-t o, programmable value. 14.2.5 block diagram figure 14-2 provides a block diagram of the adc module
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 248 freescale semiconductor figure 14-2. adc block diagram 14.3 external signal description the adc module supports up to 28 se parate analog inputs. it also re quires four supply/reference/ground connections. table 14-2. signal properties name function ad27?ad0 analog channel inputs v refh high reference voltage v refl low reference voltage v ddad analog power supply v ssad analog ground ad0 ? ? ? ad27 v refh v refl advin adch control sequencer initialize sample convert transfer abort clock divide adck 2 async clock gen bus clock altclk adiclk adiv adack adco adlsmp adlpc mode complete data registers sar converter compare value registers compare value sum aien coco interrupt aien coco adtrg 1 2 1 2 mcu stop adhwt logic acfgt 3 compare true 3 compare true adc1cfg adc1sc1 adc1sc2
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 249 14.3.1 analog power (v ddad ) the adc analog portion uses v ddad as its power connection. in some packages, v ddad is connected internally to v dd . if externally available, connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. 14.3.2 analog ground (v ssad ) the adc analog portion uses v ssad as its ground connection. in some packages, v ssad is connected internally to v ss . if externally available, connect the v ssad pin to the same voltage potential as v ss . 14.3.3 voltage reference high (v refh ) v refh is the high reference voltage for the converter . in some packages, v refh is connected internally to v ddad . if externally available, v refh may be connected to the same potential as v ddad , or may be driven by an external source th at is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). 14.3.4 voltage reference low (v refl ) v refl is the low reference voltage for the converter. in some packages, v refl is connected internally to v ssad . if externally available, connect the v refl pin to the same voltage potential as v ssad . 14.3.5 analog channel inputs (adx) the adc module supports up to 28 separate analog input s. an input is selected for conversion through the adch channel select bits. 14.4 register definition these memory mapped registers contro l and monitor operation of the adc: ? status and control register, adc1sc1 ? status and control register, adc1sc2 ? data result registers, adc1rh and adc1rl ? compare value registers, adc1cvh and adc1cvl ? configuration register, adc1cfg ? pin enable registers, apctl1, apctl2, apctl3 14.4.1 status and control register 1 (adc1sc1) this section describes the function of the adc status and control register ( adc1sc1). writing adc1sc1 aborts the current c onversion and initiates a new c onversion (if the adch bits are equal to a value other than all 1s).
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 250 freescale semiconductor 7654 3 210 rcoco aien adco adch w reset:0001 1 111 = unimplemented or reserved figure 14-3. status and control register (adc1sc1) table 14-3. adc1sc1 register field descriptions field description 7 coco conversion co mplete flag ? the coco flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (acfe = 0). when the compare function is enabled (acfe = 1) the coco flag is set upon completion of a conversion only if the compare result is true. this bit is cleared whenever adc1sc1 is written or whenever adc1rl is read. 0 conversion not completed 1 conversion completed 6 aien interrupt enable ? aien is used to enable conversion comp lete interrupts. when coco becomes set while aien is high, an interrupt is asserted. 0 conversion complete interrupt disabled 1 conversion complete interrupt enabled 5 adco continuous conversion enable ? adco is used to enable continuous conversions. 0 one conversion following a write to the adc1sc1 when software triggered operation is selected, or one conversion following assertion of adhwt when hardware triggered operation is selected. 1 continuous conversions initiated following a write to adc1sc1 when software triggered operation is selected. continuous conversions are initiated by an adhwt event when hardware triggered operation is selected. 4:0 adch input channel select ? the adch bits form a 5-bit field which is used to select one of the input channels. the input channels are detailed in figure 14-4 . the successive approximation converter subsystem is turned off when the channel select bits are all set to 1. this feature allows for explicit di sabling of the adc and isolation of the input channel from all sources. terminating continuous conversions this way will prevent an additional, single conversion from being performed. it is not necessary to set the channel select bits to a ll 1s to place the adc in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. figure 14-4. input channel select adch input select adch input select 00000 ad0 10000 ad16 00001 ad1 10001 ad17 00010 ad2 10010 ad18 00011 ad3 10011 ad19 00100 ad4 10100 ad20 00101 ad5 10101 ad21 00110 ad6 10110 ad22 00111 ad7 10111 ad23
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 251 14.4.2 status and control register 2 (adc1sc2) the adc1sc2 register is used to control the compare function, convers ion trigger and conversion active of the adc module. figure 14-5. status and control register 2 (adc1sc2) 01000 ad8 11000 ad24 01001 ad9 11001 ad25 01010 ad10 11010 ad26 01011 ad11 11011 ad27 01100 ad12 11100 reserved 01101 ad13 11101 v refh 01110 ad14 11110 v refl 01111 ad15 11111 module disabled 7654 3 210 radact adtrg acfe acfgt 00 r 1 1 bits 1 and 0 are reserved bits that must always be written to 0. r 1 w reset:0000 0 000 = unimplemented or reserved table 14-4. adc1sc2 register field descriptions field description 7 adact conversion active ? adact indicates that a conversion is in progress. adact is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 conversion not in progress 1 conversion in progress 6 adtrg conversion trigger select ? adtrg is used to select the type of trigger to be used for initiating a conversion. two types of trigger are selectable: software trigger a nd hardware trigger. when software trigger is selected, a conversion is initiated following a write to adc1sc1. when hardware trigger is selected, a conversion is initiated following the assertion of the adhwt input. 0 software trigger selected 1 hardware trigger selected figure 14-4. input channel select (continued) adch input select adch input select
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 252 freescale semiconductor 14.4.3 data result hi gh register (adc1rh) adc1rh contains the upper two bits of the result of a 10-bit conversion. when configured for 8-bit conversions both adr8 and adr9 are equal to zer o. adc1rh is updated each time a conversion completes except when automatic compare is enable d and the compare condition is not met. in 10-bit mode, reading adc1rh prevents th e adc from transferring subseque nt conversion results into the result registers until adc1rl is rea d. if adc1rl is not read until after the next conversion is completed, then the intermediate conversion result will be lost . in 8-bit mode there is no interlocking with adc1rl. in the case that the mode bits are cha nged, any data in adc1rh becomes invalid. 14.4.4 data result lo w register (adc1rl) adc1rl contains the lower eight bits of the result of a 10-bit conversi on, and all eight bits of an 8-bit conversion. this register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, reading adc1rh prevents the adc from transferring subsequent conversion results into the re sult registers until adc1rl is read. if adc1rl is not read until the after next convers ion is completed, then the intermedia te conversion results will be lost. in 8-bit mode, there is no interlocking with adc1rh . in the case that the mo de bits are changed, any data in adc1rl becomes invalid. 5 acfe compare function enable ? acfe is used to enable the compare function. 0 compare function disabled 1 compare function enabled 4 acfgt compare function greater than enable ? acfgt is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. the compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 compare triggers when input is less than compare level 1 compare triggers when input is greater than or equal to compare level 7 6543210 r 0 0 0 0 0 0 adr9 adr8 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 14-6. data result high register (adc1rh) table 14-4. adc1sc2 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 253 14.4.5 compare value high register (adc1cvh) this register holds the upper two bits of the 10-bit compare value. these bits are compared to the upper two bits of the result following a conversion in 10-bi t mode when the compare function is enabled.in 8-bit operation, adc1cvh is not used during compare. 14.4.6 compare value low register (adc1cvl) this register holds the lower 8 bits of the 10-bit comp are value, or all 8 bits of the 8-bit compare value. bits adcv7:adcv0 are compared to th e lower 8 bits of the result following a conve rsion in either 10-bit or 8-bit mode. 14.4.7 configuration register (adc1cfg) adc1cfg is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. 7 6543210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 14-7. data result low register (adc1rl) 7654 3 210 r0 0 0 0 adcv9 adcv8 w reset:0000 0 000 = unimplemented or reserved figure 14-8. compare valu e high register (adc1cvh) 7 6543210 r adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 w reset: 0 0 0 0 0 0 0 0 figure 14-9. compare value low register(adc1cvl)
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 254 freescale semiconductor 7654 3 210 r adlpc adiv adlsmp mode adiclk w reset:0000 0 000 figure 14-10. configuration register (adc1cfg) table 14-5. adc1cfg register field descriptions field description 7 adlpc low power configuration ? adlpc controls the speed and po wer configuration of the successive approximation converter. this is used to optimize powe r consumption when higher sample rates are not required. 0 high speed configuration 1 low power configuration: {fc31}the power is reduced at the expense of maximum clock speed. 6:5 adiv clock divide select ? adiv select the divide ratio used by the adc to generate the internal clock adck. ta b l e 1 4 - 6 shows the available clock configurations. 4 adlsmp long sample time configuration ? adlsmp selects between long and short sample time. this adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if hi gh conversion rates are not required. 0 short sample time 1 long sample time 3:2 mode conversion mode selection ? mode bits are used to select between 10- or 8-bit operation. see table 14-7 . 1:0 adiclk input clock select ? adiclk bits select the input clock source to generate the internal clock adck. see ta b l e 1 4 - 8 . table 14-6. clock divide select adiv divide ratio clock rate 00 1 input clock 01 2 input clock 2 10 4 input clock 4 11 8 input clock 8 table 14-7. conversion modes mode mode description 00 8-bit conversion (n=8) 01 reserved 10 10-bit conversion (n=10) 11 reserved
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 255 14.4.8 pin control 1 register (apctl1) the pin control registers are used to disable the i/ o port control of mcu pins used as analog inputs. apctl1 is used to control the pins asso ciated with channels 0?7 of the adc module. table 14-8. input clock select adiclk selected clock source 00 bus clock 01 bus clock divided by 2 10 alternate clock (altclk) 11 asynchronous clock (adack) 7654 3 210 r adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 w reset:0000 0 000 figure 14-11. pin control 1 register (apctl1) table 14-9. apctl1 register field descriptions field description 7 adpc7 adc pin control 7 ? adpc7 is used to control the pin associated with channel ad7. 0 ad7 pin i/o control enabled 1 ad7 pin i/o control disabled 6 adpc6 adc pin control 6 ? adpc6 is used to control the pin associated with channel ad6. 0 ad6 pin i/o control enabled 1 ad6 pin i/o control disabled 5 adpc5 adc pin control 5 ? adpc5 is used to control the pin associated with channel ad5. 0 ad5 pin i/o control enabled 1 ad5 pin i/o control disabled 4 adpc4 adc pin control 4 ? adpc4 is used to control the pin associated with channel ad4. 0 ad4 pin i/o control enabled 1 ad4 pin i/o control disabled 3 adpc3 adc pin control 3 ? adpc3 is used to control the pin associated with channel ad3. 0 ad3 pin i/o control enabled 1 ad3 pin i/o control disabled 2 adpc2 adc pin control 2 ? adpc2 is used to control the pin associated with channel ad2. 0 ad2 pin i/o control enabled 1 ad2 pin i/o control disabled
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 256 freescale semiconductor 14.4.9 pin control 2 register (apctl2) apctl2 is used to control ch annels 8?15 of the adc module. 1 adpc1 adc pin control 1 ? adpc1 is used to control the pin associated with channel ad1. 0 ad1 pin i/o control enabled 1 ad1 pin i/o control disabled 0 adpc0 adc pin control 0 ? adpc0 is used to control the pin associated with channel ad0. 0 ad0 pin i/o control enabled 1 ad0 pin i/o control disabled 7654 3 210 r adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 w reset:0000 0 000 figure 14-12. pin control 2 register (apctl2) table 14-10. apctl2 register field descriptions field description 7 adpc15 adc pin control 15 ? adpc15 is used to control the pin associated with channel ad15. 0 ad15 pin i/o control enabled 1 ad15 pin i/o control disabled 6 adpc14 adc pin control 14 ? adpc14 is used to control the pin associated with channel ad14. 0 ad14 pin i/o control enabled 1 ad14 pin i/o control disabled 5 adpc13 adc pin control 13 ? adpc13 is used to control the pin associated with channel ad13. 0 ad13 pin i/o control enabled 1 ad13 pin i/o control disabled 4 adpc12 adc pin control 12 ? adpc12 is used to control the pin associated with channel ad12. 0 ad12 pin i/o control enabled 1 ad12 pin i/o control disabled 3 adpc11 adc pin control 11 ? adpc11 is used to control the pin associated with channel ad11. 0 ad11 pin i/o control enabled 1 ad11 pin i/o control disabled 2 adpc10 adc pin control 10 ? adpc10 is used to control the pin associated with channel ad10. 0 ad10 pin i/o control enabled 1 ad10 pin i/o control disabled table 14-9. apctl1 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 257 14.4.10 pin control 3 register (apctl3) apctl3 is used to control ch annels 16?23 of the adc module. 1 adpc9 adc pin control 9 ? adpc9 is used to control the pin associated with channel ad9. 0 ad9 pin i/o control enabled 1 ad9 pin i/o control disabled 0 adpc8 adc pin control 8 ? adpc8 is used to control the pin associated with channel ad8. 0 ad8 pin i/o control enabled 1 ad8 pin i/o control disabled 7654 3 210 r adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 w reset:0000 0 000 figure 14-13. pin control 3 register (apctl3) table 14-11. apctl3 register field descriptions field description 7 adpc23 adc pin control 23 ? adpc23 is used to control the pin associated with channel ad23. 0 ad23 pin i/o control enabled 1 ad23 pin i/o control disabled 6 adpc22 adc pin control 22 ? adpc22 is used to control the pin associated with channel ad22. 0 ad22 pin i/o control enabled 1 ad22 pin i/o control disabled 5 adpc21 adc pin control 21 ? adpc21 is used to control the pin associated with channel ad21. 0 ad21 pin i/o control enabled 1 ad21 pin i/o control disabled 4 adpc20 adc pin control 20 ? adpc20 is used to control the pin associated with channel ad20. 0 ad20 pin i/o control enabled 1 ad20 pin i/o control disabled 3 adpc19 adc pin control 19 ? adpc19 is used to control the pin associated with channel ad19. 0 ad19 pin i/o control enabled 1 ad19 pin i/o control disabled 2 adpc18 adc pin control 18 ? adpc18 is used to control the pin associated with channel ad18. 0 ad18 pin i/o control enabled 1 ad18 pin i/o control disabled table 14-10. apctl2 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 258 freescale semiconductor 14.5 functional description the adc module is disabled during re set or when the adch bits are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when idle, the module is in its lowest power state. the adc can perform an analog-to- digital conversion on any of the so ftware selectable channels. the selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result. in 8-bit mode, the selected channel voltage is c onverted by a successive approximation algorithm into a 9-bit digital result. when the conversion is completed, the result is pl aced in the data regist ers (adc1rh and adc1rl).in 10-bit mode, the result is rounded to 10 bits and pl aced in adc1rh and adc1 rl. in 8-bit mode, the result is rounded to 8 bits and pl aced in adc1rl. the conversion comple te flag (coco) is then set and an interrupt is generated if the conversion co mplete interrupt has been enabled (aien = 1). the adc module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. the compare f unction is enabled by setting the acfe bit and operates in conjunction with any of the c onversion modes and configurations. 14.5.1 clock select and divide control one of four clock sources can be selected as the cl ock source for the adc module. this clock source is then divided by a configurable valu e to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. ? the bus clock, which is e qual to the frequency at which software is executed. this is the default selection following reset. ? the bus clock divided by 2. for hi gher bus clock rates, this allows a maximum divide by 16 of the bus clock. ? altclk, as defined for this mc u (see module section introduction). ? the asynchronous clock (adack) ? this clock is generated from a clock source within the adc module. when selected as the clock source this clock remains active while the mcu is in wait or stop3 mode and allows conversions in these modes for lower noise operation. whichever clock is selecte d, its frequency must fall within the specified freque ncy range for adck. if the available clocks are too sl ow, the adc will not perform according to specifications. if th e available clocks 1 adpc17 adc pin control 17 ? adpc17 is used to control the pin associated with channel ad17. 0 ad17 pin i/o control enabled 1 ad17 pin i/o control disabled 0 adpc16 adc pin control 16 ? adpc16 is used to control the pin associated with channel ad16. 0 ad16 pin i/o control enabled 1 ad16 pin i/o control disabled table 14-11. apctl3 register field descriptions (continued) field description
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 259 are too fast, then the clock must be divided to the appropriate frequency. this divider is specified by the adiv bits and can be divide-by 1, 2, 4, or 8. 14.5.2 input select and pin control the pin control registers (apctl3, ap ctl2, and apctl1) are used to di sable the i/o port control of the pins used as analog inputs.when a pi n control register bit is set, the following conditions ar e forced for the associated mcu pin: ? the output buffer is forced to its high impedance state. ? the input buffer is disabled. a read of the i/o port returns a zero for any pin with its input buffer disabled. ? the pullup is disabled. 14.5.3 hardware trigger the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set. this source is not available on all mcus . consult the module introduction for information on the adhwt sour ce specific to this mcu. when adhwt source is available a nd hardware trigger is enabled (adt rg=1), a conversion is initiated on the rising edge of adhwt. if a conversion is in progr ess when a rising edge oc curs, the rising edge is ignored. in continuous convert confi guration, only the initial rising edge to launch continuous conversions is observed. the hardware trigger function operates in conjunction with any of the conversion modes and configurations. 14.5.4 conversion control conversions can be performed in ei ther 10-bit mode or 8-bit mode as determined by the mode bits. conversions can be initiated by either a software or hardwa re trigger. in addition, the adc module can be configured for low power operation, long sample time, continuous conve rsion, and automatic compare of the conversion result to a soft ware determined compare value. 14.5.4.1 initiating conversions a conversion is initiated: ? following a write to adc1sc1 (w ith adch bits not all 1s) if software triggered operation is selected. ? following a hardware trigger (adhwt) event if hardware triggered operation is selected. ? following the transfer of the result to the data registers when continuous conversion is enabled. if continuous conversions are enable d a new conversion is automatically initiated after the completion of the current conversion. in software triggered operati on, continuous conversions begin after adc1sc1 is written and continue until aborted. in hardware triggered operation, continuous conversions begin after a hardware trigger event a nd continue until aborted.
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 260 freescale semiconductor 14.5.4.2 completing conversions a conversion is completed when the result of the convers ion is transferred into th e data result registers, adc1rh and adc1rl. this is indicated by the setting of coco. an interrupt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a ne w result from overwriting previ ous data in adc1rh and adc1rl if the previous data is in the process of being read while in 10-bit mode (the adc1rh register has been read but the adc1rl register has not). when blocking is active, the data transfer is blocked, coco is not set, and the new result is lost. in the case of singl e conversions with the compare function enabled and the compare condition false, blocking ha s no effect and adc operation is te rminated. in all other cases of operation, when a data transfer is bl ocked, another conversion is initiated regardless of the state of adco (single or continuous conversions enabled). if single conversions are enabled, th e blocking mechanism could result in several discarded conversions and excess power consumption. to avoid this issue, the data registers must not be read after initiating a single conversion until th e conversion completes. 14.5.4.3 aborting conversions any conversion in progress will be aborted when: ? a write to adc1sc1 occurs (the current conversion will be abor ted and a new conversion will be initiated, if adch are not all 1s). ? a write to adc1sc2, adc1cfg, adc1cvh, or adc1cvl occurs. this indicates a mode of operation change has occurred and the cu rrent conversion is therefore invalid. ? the mcu is reset. ? the mcu enters stop mode with adack not enabled. when a conversion is aborted, the c ontents of the data registers, adc1rh and adc1rl, are not altered but continue to be the values tran sferred after the completion of the la st successful convers ion. in the case that the conversion was aborted by a reset, adc1 rh and adc1rl return to their reset states. 14.5.4.4 power control the adc module remains in its idle st ate until a convers ion is initiated. if adack is selected as the conversion clock source, the adack clock generator is also enabled. power consumption when active can be reduced by se tting adlpc. this results in a lower maximum value for f adck (see the electrical specifications). 14.5.4.5 total conversion time the total conversion time depends on the sample time (as determined by adlsmp), the mcu bus frequency, the conversion mode (8-bit or 10-bi t), and the frequency of the conversion clock ( f adck ). after the module becomes active, sampling of the input begi ns. adlsmp is used to select between short and long sample times.when samp ling is complete, the converter is is olated from the input channel and a successive approximation algorithm is performed to determine the digita l value of the analog signal. the
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 261 result of the conversion is transferred to ad c1rh and adc1rl upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample ti me for continuous conversions cannot be guaranteed when s hort sample is enabled (a dlsmp=0). if the bus freque ncy is less than 1/11th of the f adck frequency, precise sample ti me for continuous conversions cannot be guaranteed when long sample is enabled (adlsmp=1). the maximum total conversion time for di fferent conditions is summarized in table 14-12 . the maximum total conversion time is determined by the clock source chosen and th e divide ratio selected. the clock source is selectable by th e adiclk bits, and the divide ratio is specified by the adiv bits. for example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, th en the conversion time fo r a single conversion is: note the adck frequency must be between f adck minimum and f adck maximum to meet adc specifications. table 14-12. total conversion time vs. control conditions conversion type adiclk adlsmp m ax total conversion time single or first continuous 8-bit 0x, 10 0 20 adck cycles + 5 bus clock cycles single or first continuous 10-bit 0x, 10 0 23 adck cycles + 5 bus clock cycles single or first continuous 8-bit 0x, 10 1 40 adck cycles + 5 bus clock cycles single or first continuous 10-bit 0x, 10 1 43 adck cycles + 5 bus clock cycles single or first continuous 8-bit 11 0 5 s + 20 adck + 5 bus clock cycles single or first continuous 10-bit 11 0 5 s + 23 adck + 5 bus clock cycles single or first continuous 8-bit 11 1 5 s + 40 adck + 5 bus clock cycles single or first continuous 10-bit 11 1 5 s + 43 adck + 5 bus clock cycles subsequent continuous 8-bit; f bus > f adck xx 0 17 adck cycles subsequent continuous 10-bit; f bus > f adck xx 0 20 adck cycles subsequent continuous 8-bit; f bus > f adck /11 xx 1 37 adck cycles subsequent continuous 10-bit; f bus > f adck /11 xx 1 40 adck cycles 23 adck cyc conversion time = 8 mhz/1 number of bus cycles = 3.5 s x 8 mhz = 28 cycles 5 bus cyc 8 mhz + = 3.5 s
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 262 freescale semiconductor 14.5.5 automatic compare function the compare function can be configur ed to check for either an upper li mit or lower limit . after the input is sampled and converted, the result is added to the two?s compleme nt of the compar e value (adc1cvh and adc1cvl). when comparing to an upper limit (acfgt = 1), if the re sult is greater-than or equal-to the compare value, coco is set. when comparing to a lower limit (acfgt = 0), if the result is less than the compare value, coco is set. th e value generated by the addition of the conversion result and the two?s complement of the compare value is transferred to adc1rh and adc1rl. upon completion of a conversion while the compare f unction is enabled, if the compare condition is not true, coco is not set and no data is transferred to the result register s. an adc interrupt is generated upon the setting of coco if the adc interrupt is enabled (aien = 1). note the compare function can be used to monitor the voltage on a channel while the mcu is in either wait or stop3 mode. the adc interrupt will wake the mcu when the compare condition is met. 14.5.6 mcu wait mode operation the wait instruction puts the mcu in a lower pow er-consumption standby mode from which recovery is very fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until comp letion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion cloc k source in wait is depe ndent on the definition of altclk for this mcu. consult the module introduct ion for information on altclk specific to this mcu. a conversion complete event sets the coco and genera tes an adc interrupt to wake the mcu from wait mode if the adc interrupt is enabled (aien = 1). 14.5.7 mcu stop3 mode operation the stop instruction is used to put the mcu in a low power-consumption standby mode during which most or all clock sources on the mcu are disabled. 14.5.7.1 stop3 mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion cl ock, executing a stop instruction aborts the current conversion and pl aces the adc in its idle state. the contents of adc1rh and adc1rl are unaffected by stop3 mode.after exit ing from stop3 mode, a so ftware or hardware tr igger is required to resume conversions.
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 263 14.5.7.2 stop3 mode with adack enabled if adack is selected as the conversion clock, the adc conti nues operation during stop3 mode. for guaranteed adc operation, the mcu?s voltage regulator must remain active during stop3 mode. consult the module introduction for configur ation information for this mcu. if a conversion is in progress when the mcu enters stop3 mode, it cont inues until completion. conversions can be initiated while the mcu is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. a conversion complete event sets the coco and gene rates an adc interrupt to wake the mcu from stop3 mode if the adc interrupt is enabled (aien = 1). note it is possible for the adc module to wake the system fr om low power stop and cause the mcu to begin consum ing run-level cu rrents without generating a system level interrupt. to prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in section 14.5.4.2, ?completing conversions ) is cleared when entering stop3 and continuing adc conversions. 14.5.8 mcu stop1 and stop2 mode operation the adc module is automatically disabled when the mcu enters either stop1 or stop2 mode. all module registers contain their reset valu es following exit from stop1 or st op2. therefore the module must be re-enabled and re-configured foll owing exit from stop1 or stop2. 14.6 initialization information this section gives an example which provides some basic direction on how a us er would initialize and configure the adc module. the user has the flexibility of choosing between configuring the module for 8-bit or 10-bit resolution, single or continuous conve rsion, and a polled or interrupt approach, among many other options. refer to table 14-6 , table 14-7 , and table 14-8 for information used in this example. note hexadecimal values designated by a pr eceding 0x, binary values designated by a preceding %, and decimal va lues have no preceding character. 14.6.1 adc module in itialization example 14.6.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. update the configuration register (adccfg) to select the input clock source and the divide ratio used to generate the internal cloc k, adck. this register is also used for sele cting sample time and low-power configuration.
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 264 freescale semiconductor 2. update status and control regi ster 2 (adcsc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. update status and control regist er 1 (adcsc1) to select whethe r conversions will be continuous or completed only once, and to en able or disable conversion comple te interrupts. the input channel on which conversions will be performed is also selected here. 14.6.1.2 pseudo ? code example in this example, the adc module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, wher e the internal ad ck clock will be derived from the bus clock divided by 1. adccfg = 0x98 (%10011000) bit 7 adlpc 1 configures for low pow er (lowers maximum clock speed) bit 6:5 adiv 00 sets the adck to the input clock 1 bit 4 adlsmp 1 configures for long sample time bit 3:2 mode 10 sets mode at 10-bit conversions bit 1:0 adiclk 00 selects bus cl ock as input clock source adcsc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress bit 6 adtrg 0 software trigger selected bit 5 acfe 0 compare function disabled bit 4 acfgt 0 not used in this example bit 3:2 00 unimplemented or reserved, always reads zero bit 1:0 00 reserved for internal use; always write zero adcsc1 = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes bit 6 aien 1 conversion complete interrupt enabled bit 5 adco 0 one conversion only (c ontinuous conversions disabled) bit 4:0 adch 00001 input channel 1 se lected as adc input channel adcrh/l = 0xxx holds results of conversion. read high byte (adcrh ) before low byte (adcrl) so that conversion data cannot be overwritten with data from the next conversion. adccvh/l = 0xxx holds compare value when compare function enabled apctl1=0x02 ad1 pin i/o control disabled. all other ad pins remain general purpose i/o pins apctl2=0x00 all other ad pins remain general purpose i/o pins
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 265 figure 14-14. initialization flowchart for example 14.7 application information this section contains information for using the adc module in applic ations. the adc has been designed to be integrated into a microcont roller for use in embedded cont rol applications requiring an a/d converter. 14.7.1 external pins and routing the following sections discuss the external pins associated with th e adc module and how they should be used for best results. 14.7.1.1 analog supply pins the adc module has analog power and ground supplies (v ddad and v ssad ) which are available as separate pins on some devi ces. on other devices, v ssad is shared on the same pin as the mcu digital v ss , and on others, both v ssad and v ddad are shared with the mcu digital supply pins. in these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolat ion between the supplies is maintained. when available on a separate pin, both v ddad and v ssad must be connected to th e same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. yes no reset initialize adc adccfg = $98 adcsc1 = $41 adcsc2 = $00 check coco=1? read adcrh then adcrl to clear coco bit continue
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 266 freescale semiconductor in cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the v ssad pin. this should be the only ground connection between these supplies if possible. the v ssad pin makes a good single point ground location. 14.7.1.2 analog reference pins in addition to the analog supplies, the adc module ha s connections for two reference voltage inputs. the high reference is v refh , which may be shared on the same pin as v ddad on some devices. the low reference is v refl , which may be shared on the same pin as v ssad on some devices. when available on a separate pin, v refh may be connected to the same potential as v ddad , or may be driven by an external source th at is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). when available on a separate pin, v refl must be connected to the same voltage potential as v ssad . both v refh and v refl must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current dema nd is a 0.1 f capacitor with good high fre quency characteristics. this capacitor is connected between v refh and v refl and must be placed as ne ar as possible to the packag e pins. resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. inductance in this path must be minimum (parasitic only). 14.7.1.3 analog input pins the external analog inputs ar e typically shared with di gital i/o pins on mcu devi ces. the pin i/o control is disabled by setting the appropriate control bit in one of the pin cont rol registers. conversions can be performed on inputs without the associated pin control register bit set. it is recommended that the pin control register bit always be set when using a pin as an analog i nput. this avoids problems with contention because the output buffer will be in its high impedan ce state and the pullup is disabled. also, the input buffer draws dc current when its input is not at either v dd or v ss . setting the pin contro l register bits for all pins used as analog inputs should be done to achieve lowest operating current. empirical data shows that capacito rs on the analog inputs improve perfor mance in the presence of noise or when the source impeda nce is high. use of 0.01 f capacitors with good high- frequency characteristics is sufficient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to $3ff (full scale 10-bit representation) or $ff (full scale 8-bit re presentation). if the input is equal to or less than v refl , the converter circuit converts it to $000. input voltages between v refh and v refl are straight-line linear c onversions. there will be a brief current associated with v refl when the sampling capacitor is charging. the input is sampled for 3.5 cycles of the adck source when adlsmp is low, or 23.5 cycles when adlsmp is high. for minimal loss of accuracy due to curr ent injection, pins adjacent to th e analog input pins should not be transitioning during conversions.
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 267 14.7.2 sources of error several sources of error exist for a/d conversions . these are discussed in the following sections. 14.7.2.1 sampling error for proper conversions, the input mu st be sampled long eno ugh to achieve the prope r accuracy. given the maximum input resistance of approximately 7k and input capacitance of a pproximately 5.5 pf, sampling to within 1/4 lsb (at 10-bit resolution) can be achieved with in the minimum sample window (3.5 cycles @ 8 mhz maximum adck frequency) provided the re sistance of the external analog source (r as ) is kept below 5 k . higher source resistances or higher-accuracy sampli ng is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 14.7.2.2 pin leakage error leakage on the i/o pins can cause conversion erro r if the external analog source resistance (r as ) is high. if this error cannot be tolera ted by the application, keep r as lower than v ddad /(2 n *i leak ) for less than 1/4 lsb leakage error (n = 8 in 8-bi t mode or 10 in 10-bit mode). 14.7.2.3 noise-induced errors system noise which occurs during the sample or conversion process can affe ct the accuracy of the conversion. the adc accuracy numbers are guaranteed as specified only if the following conditions are met: ? there is a 0.1 f low-esr capacitor from v refh to v refl . ? there is a 0.1 f low-esr capacitor from v ddad to v ssad . ? if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v ddad to v ssad . ?v ssad (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. ? operate the mcu in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (har dware or software triggered conversions) the adc conversion. ? for software triggered convers ions, immediately follow the write to the adc1sc1 with a wait instruction or stop instruction. ? for stop3 mode operation, select adack as th e clock source. operation in stop3 reduces v dd noise but increases effective conve rsion time due to stop recovery. ? there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where ex ternal system activity causes radiat ed or conducted noi se emissions or excessive v dd noise is coupled into the adc. in these situ ations, or when the mcu cannot be placed in wait or stop3 or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: ? place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssad (this will improve noise issues but will affect sample ra te based on the external analog source resistance).
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 268 freescale semiconductor ? average the result by converti ng the analog input many times in succession and dividing the sum of the results. four samples are requi red to eliminate the effect of a 1 lsb , one-time error. ? reduce the effect of synchronous noise by ope rating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 14.7.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). each step ideally has the same height (1 code) and width. the width is defined as the de lta between the transition points to one code and the next. the ideal code width fo r an n bit converter (in this case n can be 8 or 10), defined as 1 lsb , is: 1 lsb = (v refh - v refl ) / 2 n eqn. 14-2 there is an inherent quantization e rror due to the digitizati on of the result. for 8-bi t or 10-bit conversions the code will transition when the voltage is at th e midpoint between the point s where the straight line transfer function is exactly repres ented by the actual transfer functi on. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code width of the first ($000) conversion is only 1/2 lsb and the code width of the last ($ff or $3ff) is 1.5 lsb . 14.7.2.5 linearity errors the adc may also exhibit non-linearity of several fo rms. every effort has been made to reduce these errors but the system should be aware of them beca use they affect overall accuracy. these errors are: ? zero-scale error (e zs ) (sometimes called offset ) ? this error is defined as the difference between the actual code width of the first c onversion and the ideal code width (1/2 lsb ). note, if the first conversion is $001, then the difference betwee n the actual $001 code width and its ideal (1 lsb ) is used. ? full-scale error (e fs ) ? this error is defined as the differ ence between the actual code width of the last conversion and the ideal code width (1.5 lsb ). note, if the last conversion is $3fe, then the difference between the actual $3fe code width and its ideal (1 lsb ) is used. ? differential non-linearity (dnl) ? this error is de fined as the worst-case difference between the actual code width and the ideal code width for all conversions. ? integral non-linearity (inl) ? this error is defined as the highest-val ue the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its co rresponding ideal transition voltage, for all codes. ? total unadjusted error (tue) ? this error is defi ned as the difference between the actual transfer function and the ideal straight-line transfer f unction, and therefore includes all forms of error. 14.7.2.6 code jitter, non-monotonicity and missing codes analog-to-digital converters are susceptible to thr ee special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain poi nts, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is infinitesi mally smaller than the transition voltage, the
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 269 converter yields the lower code (a nd vice-versa). however, even very small amounts of system noise can cause the converter to be indete rminate (between two codes) for a range of input voltages around the transition voltage. this ra nge is normally around 1/2 lsb and will increase with noise. this error may be reduced by repeatedly samp ling the input and averaging the result . additionally the techniques discussed in section 14.7.2.3 will reduce this error. non-monotonicity is defined as when, except for code jitter, the convert er converts to a lower code for a higher input voltage. missing codes are those values which are never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and to have no missing codes.
analog-to-digital converter (s08adc10v1) mc9s08ac16 series data sheet, rev. 8 270 freescale semiconductor
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 271 chapter 15 development support 15.1 introduction development support systems in the hcs08 include the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provides a singl e-wire debug interface to the target mcu that provides a convenient inte rface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allo ws non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoint s, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through comma nds fed into the target mcu vi a the single-wire background debug interface. the debug module provides a means to sel ectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. the alternate bdc clock so urce for mc9s08ac16 series is the icglclk. see chapter 8, ?internal clock generator (s08icgv4) ? for more information about icgclk and how to select clock sources.
development support mc9s08ac16 series data sheet, rev. 8 272 freescale semiconductor 15.1.1 features features of the bdc module include: ? single pin for mode selecti on and background communications ? bdc registers are not located in the memory map ? sync command to determine target communications rate ? non-intrusive commands for memory access ? active background mode comma nds for cpu register access ? go and trace1 commands ? background command can wake cpu from stop or wait modes ? one hardware address br eakpoint built into bdc ? oscillator runs in stop mode, if bdc enabled ? cop watchdog disabled while in active background mode features of the ice system include: ? two trigger comparators: two address + read/w rite (r/w) or one full address + data + r/w ? flexible 8-word by 16-bit fi fo (first-in, first-out) buffe r for capture information: ? change-of-flow addresses or ? event-only data ? two types of breakpoints: ? tag breakpoints for instruction opcodes ? force breakpoints for any address access ? nine trigger modes: ? basic: a-only, a or b ? sequence: a then b ? full: a and b data, a and not b data ? event (store data): event- only b, a then event-only b ? range: inside range (a address b), outside range (address < a or address > b) 15.2 background debug controller (bdc) all mcus in the hcs08 family co ntain a single-wire background debug in terface that supports in-circuit programming of on-chip nonvolatile me mory and sophisticated non-intrus ive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: ? active background mode commands require that the target mcu is in active background mode (the user program is not running). ac tive background mode commands al low the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode.
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 273 ? non-intrusive commands can be executed at any time even while the user?s program is running. non-intrusive commands allo w a user to read or wr ite mcu memory locations or access status and control registers within the background debug controller. typically, a relatively s imple interface pod is used to translat e commands from a host computer into commands for the custom serial interface to the single-wire bac kground debug system. depending on the development tool vendor, this interface pod may use a sta ndard rs-232 serial port, a parallel printer port, or some other type of communicati ons such as a universal serial bu s (usb) to communicate between the host pc and the pod. the pod typically connects to th e target system with ground, the bkgd pin, reset , and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target syst em or to control startup of a target system before the on-chip nonvolatile memory has be en programmed. sometimes v dd can be used to allow the pod to use power from the target system to a void the need for a separa te power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 15-1. bdm tool connector 15.2.1 bkgd pin description bkgd is the single-wire backgr ound debug interface pin. the primary function of this pin is for bidirectional serial communi cation of active background mode commands and data. during reset, this pin is used to select between starting in active backgr ound mode or starting the us er?s application program. this pin is also used to request a timed sync respons e pulse to allow a host deve lopment tool to determine the correct clock frequency for b ackground debug serial communications. bdc serial communications use a cu stom serial protocol first intr oduced on the m68hc12 family of microcontrollers. this protocol a ssumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is in itiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most significant bit first (msb first). for a detailed descript ion of the communications protocol, refer to section 15.2.2, ?communication details .? if a host is attempting to communi cate with a target mcu that ha s an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync res ponse signal from wh ich the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no ex ternal pullup resistor is required. unlike typical open-drain pins, the ex ternal rc time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. the custom prot ocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmfu l drive level conflicts. refer to section 15.2.2, ?communication details ,? for more detail. 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
development support mc9s08ac16 series data sheet, rev. 8 274 freescale semiconductor when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode . when a debug pod is connected to bkgd it is possible to force the mcu into active background mode after reset. the speci fic conditions for forci ng active background depend upon the hcs08 derivative (refer to the introduction to this developm ent support section). it is not necessary to reset the target mcu to communi cate with it through the background debug interface. 15.2.2 communication details the bdc serial interface requires the external contro ller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external cont roller provides this fall ing edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an extern al controller or by the mcu. data is transferred msb first at 16 bdc clock cycles pe r bit (nominal speed). th e interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecti ng the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and c ontrol register allows th e user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or lo w level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 275 figure 15-2 shows an external host trans mitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0- to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively driv es the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to tr eat the line as an open-drain signal during this period. figure 15-2. bdc ho st-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
development support mc9s08ac16 series data sheet, rev. 8 276 freescale semiconductor figure 15-3 shows the host receiving a logic 1 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived star t of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brie f active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level a bout 10 cycles after it started the bit time. figure 15-3. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 277 figure 15-4 shows the host receiving a logic 0 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by th e target mcu. the host initiates the bit time but the target hcs08 finishes it. because the target wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 bdc clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 15-4. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
development support mc9s08ac16 series data sheet, rev. 8 278 freescale semiconductor 15.2.3 bdc commands bdc commands are sent se rially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-first using a cust om bdc communicat ions protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 15-1 shows all hcs08 bdc commands, a shorthand de scription of their codi ng structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 15-1 to describe the coding stru cture of the bdc commands. commands begin with an 8-bit hexadeci mal command code in the host-to-target direction (most signi ficant bit first) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in th e target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target -to-host direction (fro m bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-tar get direction (for bdcb kpt breakpoint register)
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 279 table 15-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss r ead bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd r ead a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/ rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusiv e c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. re port status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
development support mc9s08ac16 series data sheet, rev. 8 280 freescale semiconductor the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to us e for bdc communications until afte r it has analyzed the response to the sync command. to issue a sync command, the host: ? drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscill ator/64 or the self-clocked rate/64.) ? drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) ? removes all drive to the bkgd pin so it reverts to high impedance ? monitors the bkgd pin for the sync response pulse the target, upon detectin g the sync request fr om the host (which is a much longer low time than would ever occur during norma l bdc communications): ? waits for bkgd to re turn to a logic high ? delays 16 cycles to allow the host to stop driving the high speedup pulse ? drives bkgd low for 128 bdc clock cycles ? drives a 1-cycle high speedup pulse to force a fast rise time on bkgd ? removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync res ponse pulse and determines the correct speed for subsequent bdc communications. typically, the hos t can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 15.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware br eakpoint that compares th e cpu address bus to a 16-bit match value in the bdcbkpt register. this brea kpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to ente r active background mode at the first instruction boundary following any access to the breakpoint addres s. the tagged breakpoint causes the instruction opcode at the breakpoint addr ess to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten ) control bit in the bdc status and control re gister (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is di sabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg ) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the bdc module.
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 281 15.3 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have be en built onto the chip with the mcu. the debug system consists of an 8-stage fifo that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status regist ers that are accessible in the user?s memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug module?s functions are used during development, a nd user programs rarely access any of the control and status registers for the debug modul e. the one exception is that the debug system can provide the means to implement a fo rm of rom patching. this topic is discussed in greater detail in section 15.3.6, ?hardware breakpoints .? 15.3.1 comparators a and b two 16-bit comparators (a and b) ca n optionally be qualified with the r/w signal and an opcode tracking circuit. separate control bits a llow you to ignore r/w for each compar ator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opc ode at the specified address is actually executed as opposed to onl y being read from memory into th e instruction queue. the comparators are also capable of magnitude comp arisons to support the inside range and outside range trigger modes. comparators are disabled temp orarily during all bdc accesses. the a comparator is always associated with the 16- bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. because the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address pl us data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpu?s write data bus is used. otherwise, the cpu?s read data bus is used. the currently selected trigger mode determines what the debugger logi c does when a comparator detects a qualified match condition. a match can cause: ? generation of a breakpoint to the cpu ? storage of data bus values into the fifo ? starting to store change-of-flow addre sses into the fifo (begin type trace) ? stopping the storage of change-of-flow a ddresses into the fifo (end type trace) 15.3.2 bus capture informat ion and fifo operation the usual way to use the fifo is to setup the tr igger mode and other cont rol options, then arm the debugger. when the fifo has filled or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo . status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the inform ation is shifted by one position and
development support mc9s08ac16 series data sheet, rev. 8 282 freescale semiconductor the host must perform ((8 ? cnt) ? 1) dummy reads of the fifo to advance it to the first significant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-flow addresses. in these cases, read dbgfh then dbgfl to get one coherent word of info rmation out of th e fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see section 15.3.5, ?trigger modes ? ), 8-bit data information is stored in to the fifo. in these cases, the high- order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. ea ch time dbgfl is read, the fifo is shifted so the next data value is av ailable through the fifo data port at dbgfl. in trigger modes where the fifo is storing change -of-flow addresses, there is a delay between cpu addresses and the input side of th e fifo. because of this delay, if the trigger event itself is a change-of-flow address or a change-o f-flow address appears during the ne xt two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. the fifo can also be used to generate a profile of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the addr ess of the most-recently fetched opcode to be saved in the fifo. to use the prof iling feature, a host debugger would re ad addresses out of the fifo by reading dbgfh then dbgfl at regul ar periodic intervals. the first eight values would be discarded because they correspond to the eight dbgfl reads needed to initially fill the fifo. additional periodic reads of dbgfh and dbgfl return de layed information about executed instructions so the host debugger can develop a profile of exec uted instruction addresses. 15.3.3 change-of-flow information to minimize the amount of informati on stored in the fifo, only informat ion related to in structions that cause a change to the normal sequential execution of in structions is stored. w ith knowledge of the source and object code program stor ed in the target system, an external debugger system can reconstruct the path of execution through many instruct ions from the change -of-flow information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the a ddress of the conditional br anch opcode). because bra and brn instructions are not conditional, these events do not cause change-o f-flow information to be stored in the fifo. indirect jmp and jsr instruct ions use the current contents of the h: x index register pair to determine the destination address, so the debug system stores the r un-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-flow information. 15.3.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruc tion opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because a ny change-of-flow from a jump, bran ch, subroutine call, or interrupt causes some instructions that have been fetched into the in struction queue to be thrown away without being executed.
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 283 a force-type breakpoint wa its for the current instruction to fi nish and then acts upon the breakpoint request. the usual action in respons e to a breakpoint is to go to ac tive background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminolo gy is used in two contexts within the debug module. the first context refers to breakpoint requests from the debug module to the cp u. the second refers to match signals from the comparators to the debugger control logi c. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opc ode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executi ng the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is se parate opcode tracking logic for each comparator so more than one compare event can be tracke d through the instruction queue at a time. 15.3.5 trigger modes the trigger mode controls the overa ll behavior of a debug run. the 4-bi t trg field in th e dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt regi ster, the output of the comparator must propagate through an opcode tr acking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fi fo begins storing data wh en the qualified trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed unt il the qualified trigger is detected (end trigger). a debug run is started by wr iting a 1 to the arm bit in the dbgc register, which sets the armf flag and clears the af and bf flags and the cnt bits in dbgs. a be gin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to arm or dbgen in dbgc. in all trigger modes except event- only modes, the fifo stores change -of-flow addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only tri gger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not n ecessary to use r/w in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. it would also be unusual to specify trgsel = 1 while using a full m ode trigger because the opcode value is normally known at a particular address. the following trigger mode descripti ons only state the primary comparator conditions that lead to a trigger. either comparator can usually be further quali fied with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the si gnal from the comparator with optional r/w qualification is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request.
development support mc9s08ac16 series data sheet, rev. 8 284 freescale semiconductor a-only ? trigger when the address matc hes the value in comparator a a or b ? trigger when the address matches either the value in comparator a or the value in comparator b a then b ? trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any num ber of cycles after the a match and before the b match. a and b data (full mode) ? this is called a full mode because address, data, a nd r/w (optionally) must match within the same bus cycle to cause a tri gger event. comparator a ch ecks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. a and not b data (full mode) ? address must match comparator a, data must not match the low half of comparator b, and r/w mu st match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. event-only b (store data) ? trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) ? after the address has matched the value in comparator a, a trigger event occurs each time the address ma tches the value in comparator b. tr igger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) ? a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ? a trigger occurs when the a ddress is either less than the value in comparator a or greater than the value in comparator b.
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 285 15.3.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in section 15.3.5, ?trigger modes ,? to be used to gene rate a hardware breakpoint request to the cpu. tag in dbgc controls whether the breakpoint reque st will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it ente rs the instruction queue. if a tagged opcode reaches the end of the pipe, th e cpu executes a bgnd in struction to go to active background mode rather than execut ing the tagged opcode. a force-type breakpoint causes the cpu to finish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 15.4 register definition this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summar y in the device overview chapter of this data sheet for the absolute address assignments for all dbg regist ers. this section refers to regi sters and control bits only by their names. 15.4.1 bdc registers and control bits the bdc has two registers: ? the bdc status and control regist er (bdcscr) is an 8-bit regist er containing cont rol and status bits for the background debug controller. ? the bdc breakpoint match register (bdcbkpt ) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have a ddresses and cannot be a ccessed by user programs). some of the bits in the bdcscr ha ve write limitations; otherwise, thes e registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents th e ambiguous condition of the contro l bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be wr itten by the write_control serial bdc command. the clock switch (clksw) control bit may be r ead or written at any time.
development support mc9s08ac16 series data sheet, rev. 8 286 freescale semiconductor 15.4.1.1 bdc status and c ontrol register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 15-5. bdc status and control register (bdcscr) table 15-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ? typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the deb ug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ? this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ? if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ? when fts = 1, a breakpoint is request ed whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagg ed. if this tagged opcode ever reache s the end of the instruction queue, the cpu enters active background mode ra ther than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ? clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 287 15.4.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hard ware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and c onfigure the breakpoint logi c. dedicated serial bdc commands (read_bkpt and write_bk pt) are used to read and writ e the bdcbkpt register but is not accessible to user programs b ecause it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for a dditional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 15.2.4, ?bdc hardware breakpoint .? 15.4.2 system background debug force reset register (sbdfr) this register contains a single write-only contro l bit. a serial background mode command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. 2 ws wait or stop status ? when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force t he target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a backgro und command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status ? this status bit is set if a memory a ccess command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically , the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not conflict with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status ? this status bit is not used in the mc9s08ac16 series because it does not have any slow access memory. 0 memory access did not conflict with a slow memory access 1 memory access command failed because cpu was not finished with a slow memory access table 15-2. bdcscr register fi eld descriptions (continued) field description
development support mc9s08ac16 series data sheet, rev. 8 288 freescale semiconductor figure 15-6. system background debug force reset register (sbdfr) 15.4.3 dbg registers and control bits the debug module includes nine bytes of register spac e for three 16-bit register s and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal applic ation programs. these re gisters are rarely if ever accessed by normal user application pr ograms with the possible ex ception of a rom patching mechanism that uses the breakpoint logic. 15.4.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high- order eight bits of comparat or a. this register is forced to 0x00 at reset and can be read at a ny time or written at any time unless arm = 1. 15.4.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low- order eight bits of comparat or a. this register is forced to 0x00 at reset and can be read at a ny time or written at any time unless arm = 1. 15.4.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high- order eight bits of comparat or b. this register is forced to 0x00 at reset and can be read at a ny time or written at any time unless arm = 1. 15.4.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low- order eight bits of comparat or b. this register is forced to 0x00 at reset and can be read at a ny time or written at any time unless arm = 1. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. reset00000000 = unimplemented or reserved table 15-3. sbdfr register field description field description 0 bdfr background debug force reset ? a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forc es an mcu reset. this bit cannot be written from a user program.
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 289 15.4.3.5 debug fifo high register (dbgfh) this register provides read- only access to the high-order ei ght bits of the fifo. writes to this register have no meaning or effect. in the event- only trigger modes, the fifo only st ores data into the low-order byte of each fifo word, so this regist er is not used and will read 0x00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. 15.4.3.6 debug fifo low register (dbgfl) this register provides read- only access to the low-order ei ght bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the ne xt available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into th e fifo (high-order half of each fifo word is unused). when readi ng 8-bit words out of the fifo, simp ly read dbgfl repeatedly to get successive bytes of data from the fifo. it is n?t necessary to read dbgfh in this case. do not attempt to read data from th e fifo while it is still armed (after arming but before th e fifo is filled or armf is cleared) because the fi fo is prevented from advancing during reads of dbgfl. this can interfere with normal sequenci ng of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodical ly, external host software can develop a prof ile of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the first read. to use the profiling feature, read the fifo eight times without using the data to prime the sequence and then begi n using the data to get a delayed picture of what addresses were be ing executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode.
development support mc9s08ac16 series data sheet, rev. 8 290 freescale semiconductor 15.4.3.7 debug control register (dbgc) this register can be read or written at any time. 76543210 r dbgen arm tag brken rwa rwaen rwb rwben w reset00000000 figure 15-7. debug control register (dbgc) table 15-4. dbgc register field descriptions field description 7 dbgen debug module enable ? used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 0dbg disabled 1 dbg enabled 6 arm arm control ? controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and armf) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 0 debugger not armed 1 debugger armed 5 tag tag/force select ? controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 0 cpu breaks requested as force type requests 1 cpu breaks requested as tag type requests 4 brken break enable ? controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparat or(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fi fo becomes full. trgsel does not affect the timing of cpu break requests. 0 cpu break requests not enabled 1 triggers cause a break request to the cpu 3 rwa r/w comparison value for comparator a ? when rwaen = 1, this bit determines whether a read or a write access qualifies comparator a. when rwaen = 0, rw a and the r/w signal do not affect comparator a. 0 comparator a can only match on a write cycle 1 comparator a can only match on a read cycle 2 rwaen enable r/w for comparator a ? controls whether the level of r/w is considered for a comparator a match. 0 r/w is not used in comparison a 1 r/w is used in comparison a 1 rwb r/w comparison value for comparator b ? when rwben = 1, this bit determines whether a read or a write access qualifies comparator b. when rwben = 0, rw b and the r/w signal do not affect comparator b. 0 comparator b can match only on a write cycle 1 comparator b can match only on a read cycle 0 rwben enable r/w for comparator b ? controls whether the level of r/w is considered for a comparator b match. 0 r/w is not used in comparison b 1 r/w is used in comparison b
development support mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 291 15.4.3.8 debug trigger register (dbgt) this register can be read any time , but may be written only if arm = 0, except bits 4 and 5 are hard-wired to 0s. 76543210 r trgsel begin 00 trg3 trg2 trg1 trg0 w reset00000000 = unimplemented or reserved figure 15-8. debug trigger register (dbgt) table 15-5. dbgt regist er field descriptions field description 7 trgsel trigger type ? controls whether the match outputs from com parators a and b are qualified with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparat or a or b must propagate through the opcode tracking logic and a trigger event is on ly signalled to the fifo logi c if the opcode at the match address is actually executed. 0 trigger on access to compare address (force) 1 trigger if opcode at compare address is executed (tag) 6 begin begin/end trigger select ? controls whether the fifo starts filling at a trigger or fills in a circular manner until a trigger ends the capture of informati on. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 data stored in fifo until trigger (end trace) 1 trigger initiates data storage (begin trace) 3:0 trg[3:0] select trigger mode ? selects one of nine triggering modes, as described below. 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ? 1111 (no trigger)
development support mc9s08ac16 series data sheet, rev. 8 292 freescale semiconductor 15.4.3.9 debug status register (dbgs) this is a read-onl y status register. 76543210 r af bf armf 0 cnt3 cnt2 cnt1 cnt0 w reset00000000 = unimplemented or reserved figure 15-9. debug status register (dbgs) table 15-6. dbgs register field descriptions field description 7 af trigger match a flag ? af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 0 comparator a has not matched 1 comparator a match 6 bf trigger match b flag ? bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 0 comparator b has not matched 1 comparator b match 5 armf arm flag ? while dbgen = 1, this status bit is a read-only im age of arm in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trac e) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to arm or dbgen in dbgc. 0 debugger not armed 1 debugger armed 3:0 cnt[3:0] fifo valid count ? these bits are cleared at the start of a debu g run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping trac k of the count as information is read out of the fifo. 0000 number of valid words in fifo = no valid data 0001 number of valid words in fifo = 1 0010 number of valid words in fifo = 2 0011 number of valid words in fifo = 3 0100 number of valid words in fifo = 4 0101 number of valid words in fifo = 5 0110 number of valid words in fifo = 6 0111 number of valid words in fifo = 7 1000 number of valid words in fifo = 8
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 293 appendix a electrical characteristics and timing specifications a.1 introduction this section contains electrical and timing specifications. a.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding, the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. a.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table a-2 may affect device reliability or cause permanent damage to the de vice. for functional operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than table a-1. paramete r classifications p those parameters are guara nteed during production testi ng on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditio ns unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derive d mainly from simulations.
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 294 freescale semiconductor maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ). a.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-deter mined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or table a-2. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to + 5.8 v input voltage v in ? 0.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1 , 2 , 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the m cu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. i d 25 ma maximum current into v dd i dd 120 ma storage temperature t stg ?55 to +150 c maximum junction temperature t j 150 c
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 295 v dd and multiply by the pin current for each i/o pin. ex cept in cases of unusuall y high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resist ance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. a-2 solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations 1 and 2 iteratively for any value of t a . table a-3. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 125 c thermal resistance 1,2,3,4 1 junction temperature is a function of die si ze, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on th e board, and board thermal resistance. 2 junction to ambient natural convection 3 1s - single layer board, one signal layer 4 2s2p - four layer board, 2 signal and 2 power layers ja c/w 48-pin qfn 1s 2s2p 84 27 44-pin lqfp 1s 2s2p 73 56 32-pin lqfp 1s 2s2p 85 56 42-pin sdip 1s 2s2p 58 47
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 296 freescale semiconductor a.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling preca utions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. all esd testing is in conformit y with aec-q100 stress test qual ification for automotive grade integrated circuits. during the device qualification esd stresses we re performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametr ic and functional testing is perf ormed per the applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification. table a-4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulse per pin ? 3 machine series resistance r1 0 storage capacitance c 200 pf number of pulse per pin ? 3 latch-up minimum input voltage limit ? 2.5 v maximum input voltage limit 7.5 v table a-5. esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 ? v 2 c machine model (mm) v mm 200 ? v 3 c charge device model (cdm) v cdm 500 ? v 4c latch-up current at t a = 125 ci lat 100 ? ma
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 297 a.6 dc characteristics this section includes information about power supply requirements, i/o pin char acteristics, and power supply current in various operating modes. table a-6. dc characteristics num c parameter symbol min typ 1 max unit 1p output high voltage ? low drive (ptxdsn = 0) 5 v, i load = ?2 ma 3 v, i load = ?0.6 ma 5 v, i load = ?0.4 ma 3 v, i load = ?0.24 ma v oh v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? v output high voltage ? high drive (ptxdsn = 1) 5 v, i load = ?10 ma 3 v, i load = ?3 ma 5 v, i load = ?2 ma 3 v, i load = ?0.4 ma v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? 2p output low voltage ? low drive (ptxdsn = 0) 5 v, i load = 2 ma 3 v, i load = 0.6 ma 5 v, i load = 0.4 ma 3 v, i load = 0.24 ma v ol ? ? ? ? ? ? ? ? 1.5 1.5 0.8 0.8 v output low voltage ? high drive (ptxdsn = 1) 5 v, i load = 10 ma 3 v, i load = 3 ma 5 v, i load = 2 ma 3 v, i load = 0.4 ma ? ? ? ? ? ? ? ? 1.5 1.5 0.8 0.8 3 p output high current ? max total i oh for all ports 5v 3v i oht ? ? ? ? 100 60 ma 4 p output low current ? max total i ol for all ports 5v 3v i olt ? ? ? ? 100 60 ma 5p input high 2.7v v dd 4.5v v ih 0.70xv dd ?? v voltage; all digital inputs 4.5v v dd 5.5v v ih 0.65xv dd ?? 6 p input low voltage; all digital inputs v il ? ? 0.35 x v dd 7 p input hysteresis; all digital inputs v hys 0.06 x v dd v 8 p input leakage current; input only pins 2 |i in |?0.11 a 9 p high impedance (off-state) leakage current 2 |i oz |?0.1 1 a 10 p internal pullup resistors 3 r pu 20 45 65 k 11 p internal pulldown resistors 4 r pd 20 45 65 k 12 c input capacitance; all non-supply pins c in ?? 8pf 13 p por rearm voltage v por 0.9 1.4 2.0 v 14 d por rearm time t por 10 ? ? s
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 298 freescale semiconductor 15 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d h 4.2 4.3 4.3 4.4 4.4 4.5 v 16 p low-voltage detection threshold ? low range v dd falling v dd rising v lv d l 2.48 2.54 2.56 2.62 2.64 2.7 v 17 p low-voltage warning threshold ? high range v dd falling v dd rising v lv w h 4.2 4.3 4.3 4.4 4.4 4.5 v 18 p low-voltage warning threshold ? low range v dd falling v dd rising v lv w l 2.48 2.54 2.56 2.62 2.64 2.7 v 19 p low-voltage inhibit reset/recover hysteresis 5v 3v v hys ? ? 100 35 ? ? mv 20 p bandgap voltage reference factory trimmed at v dd = 5.0 v temp = 25 c v bg 1.185 1.202 1.215 v 21 d dc injection current 5, 6, 7, 8 |i ic | single pin limit v in > v dd 0?2ma v in < v ss 0??0.2ma total mcu limit, includes sum of all stressed pins v in > v dd 0?25ma v in < v ss 0??5ma 1 typical values are based on characterization data at 25 c unless otherwise stated. 2 measured with v in = v dd or v ss . 3 measured with v in = v ss . 4 measured with v in = v dd . 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this wi ll be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low which (would reduce overall power consumption). 6 all functional non-supply pins are internally clamped to v ss and v dd . 7 input must be current limited to the value specified. to determine the value of the requi red current-limiting resistor, calculate resistance values for positive and negative cl amp voltages, then use the larger of the two values. 8 irq does not have a clamp diode to v dd . do not drive irq above v dd . table a-6. dc characteristics (continued) num c parameter symbol min typ 1 max unit
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 299 figure a-1. typical i oh (low drive) vs v dd ?v oh at v dd = 3 v figure a-2. typical i oh (high drive) vs v dd ?v oh at v dd = 3 v ?5.0e-3 ?4.0e-3 ?3.0e-3 ?2.0e-3 ?1.0e-3 000e+0 0 0.3 0.5 0.8 0.9 1.2 1.5 v dd ?v oh (v) v supply ?v oh average of i oh i oh (a) ?40 c 25 c 125 c ?6.0e-3 ?20.0e-3 ?18.0e-3 ?16.0e-3 ?14.0e-3 ?12.0e-3 ?10.0e-3 ?8.0e-3 ?6.0e-3 ?4.0e-3 ?2.0e-3 000.0e-3 0 0.3 0.5 0.8 0.9 1.2 1.5 v supply ?v oh v dd ?v oh (v) average of i oh ?40 c 25 c 125 c i oh (a)
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 300 freescale semiconductor figure a-3. typical i oh (low drive) vs v dd ?v oh at v dd = 5 v figure a-4. typical i oh (high drive) vs v dd ?v oh at v dd = 5 v ?5.0e-3 ?4.0e-3 ?3.0e-3 ?2.0e-3 ?1.0e-3 000e+0 0.00 0.30 average of i oh ?40 c 25 c 125 c ?6.0e-3 ?7.0e-3 0.50 0.80 1.00 1.30 2.00 v dd ?v oh (v) v supply ?v oh i oh (a) ?40 c 25 c 125 c 0.00 0.30 0.50 0.80 1.00 1.30 2.00 v supply ?v oh ?30.0e-3 ?25.0e-3 ?20.0e-3 ?15.0e-3 ?10.0e-3 ?5.0e-3 000.0e+3 v dd ?v oh (v) i oh (a) average of i oh
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 301 a.7 supply current characteristics table a-7. supply current characteristics num c parameter symbol v dd (v) typ 1 1 typical values are based on characterization data at 25 c unless otherwise stated. see figure a-5 through figure a-7 for typical curves across voltage/temperature. max 2 2 values given here are preliminary estimates prior to completing characterization. unit temp ( c) 1c run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz) 3 all modules except adc active, icg configured for fb e, and does not include any dc loads on port pins ri dd 50.9881.2 4 4 every unit tested to this parameter. all other values in the max column are guaranteed by characterization. ma ?40 to 125 c 3 0.570 0.770 2c run supply current 5 measured at (cpu clock = 16 mhz, f bus = 8 mhz) 5 all modules except adc active, icg configured for fb e, and does not include any dc loads on port pins ri dd 56.84 8 6 6 every unit tested to this parameter. all other values in the max column are guaranteed by characterization. ma ?40 to 125 c 3 5.5 5.70 3p run supply current 7 measured at (cpu clock = 40 mhz, f bus = 20 mhz) 7 all modules except adc active, icg configured for fbe and does not include any dc loads on port pins ri dd 5 16.8 18.5 ma ?40 to 125 c 3 11.5 12.5 ma ?40 to 125 c 4c stop2 mode supply current s2i dd 51.36 11 20 60 4 a 0 to 70 c ?40 to 85 c ?40 to 125 c 31.05 10.5 17 50 a 0 to 70 c ?40 to 85 c ?40 to 125 c 5c stop3 mode supply current s3i dd 51.49 12 20 90 4 a 0 to 70 c ?40 to 85 c ?40 to 125 c 31.15 11 19 85 a 0 to 70 c ?40 to 85 c ?40 to 125 c 6c rti adder to stop2 or stop3 8 8 most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 3 v with f bus = 1 mhz. s23i ddrti 5300 500 500 na ?40 to 85 c ?40 to 125 c 3300 500 500 na ?40 to 85 c ?40 to 125 c 7 c lvd adder to stop3 (lvde = lvdse = 1) s3i ddlvd 5116 150 180 a ?40 to 85 c ?40 to 125 c 390 140 160 a ?40 to 85 c ?40 to 125 c 8c adder to stop3 for oscillator enabled 9 (oscsten =1) 9 values given under the following conditions: low range operat ion (range = 0) with a 32.768khz crystal, low power mode (hgo = 0), clock monitor disabled (locd = 1). s3i ddosc 5,3 5 6 8 a a ?40 to 85 c ?40 to 125 c
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 302 freescale semiconductor figure a-5. typical run i dd for fbe and fee modes, i dd vs. v dd 5.4 5.0 4.6 4.2 3.8 3.4 3.0 2.6 2.2 0 2 4 6 8 10 12 14 16 18 i dd v dd 20 mhz, adc off, fee, 25 c 20 mhz, adc off, fbe, 25 c 8 mhz, adc off, fee, 25 c 8 mhz, adc off, fbe, 25 c 1 mhz, adc off, fee, 25 c 1 mhz, adc off, fbe, 25 c note: external clock is square wave supplied by function generator. for fee mode, external reference frequency is 4
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 303 figure a-6. typical stop2 i dd figure a-7. typical stop3 i dd ?5.0e-3 ?4.0e-3 ?3.0e-3 ?2.0e-3 ?1.0e-3 000e+0 ?6.0e-3 ?7.0e-3 ?8.0e-3 1.8 2 2.5 3 3.5 4 4.5 5 stop2 i dd (a) average of measurement i dd i dd (a) v dd (v) ?40 c 25 c 55 c 85 c ?5.0e-3 ?4.0e-3 ?3.0e-3 ?2.0e-3 ?1.0e-3 000e+0 ?6.0e-3 ?7.0e-3 ?8.0e-3 1.8 2 2.5 3 3.5 4 4.5 5 stop3 i dd (a) average of measurement i dd i dd (a) v dd (v) 25 c 55 c 85 c ?40 c
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 304 freescale semiconductor a.8 adc characteristics table a-8. 5 volt 10-bit adc operating conditions characteristic conditions symb min typ 1 1 typical values assume v ddad = 5.0 v, temp = 25 c, f adck = 1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit supply voltage absolute v ddad 2.7 ? 5.5 v delta to v dd (v dd ?v ddad ) 2 2 dc potential difference. v ddad ?100 0 +100 mv ground voltage delta to v ss (v ss ?v ssad ) 2 v ssad ?100 0 +100 mv ref voltage high v refh 2.7 v ddad v ddad v ref voltage low v refl v ssad v ssad v ssad v supply current stop, reset, module off i ddad ? 0.011 1 a input voltage v adin v refl ?v refh v input capacitance c adin ?4.55.5pf input resistance r adin ?3 5k analog source resistance external to mcu 10-bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 5 10 k 8-bit mode (all valid f adck )??10 adc conversion clock frequency high speed (adlpc = 0) f adck 0.4 ? 8.0 mhz low power (adlpc = 1) 0.4 ? 4.0
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 305 figure a-8. adc input impedance equivalency diagram table a-9. 5 volt 10-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic conditions c symb min typ 1 max unit supply current adlpc = 1 adlsmp = 1 adco = 1 ti ddad ? 133 ? a supply current adlpc = 1 adlsmp = 0 adco = 1 ti ddad ? 218 ? a supply current adlpc = 0 adlsmp = 1 adco = 1 ti ddad ? 327 ? a supply current adlpc = 0 adlsmp = 0 adco = 1 ti ddad ? 582 ? a v ddad < 5.5 v p ? ? 1 ma adc asynchronous clock source t adack = 1/f adack high speed (adlpc = 0) p f adack 23.35mhz low power (adlpc = 1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp = 0) p t adc ?20?adck cycles long sample (adlsmp = 1) ? 40 ? + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 306 freescale semiconductor sample time short sample (adlsmp = 0) p t ads ?3.5?adck cycles long sample (adlsmp = 1) ? 23.5 ? total unadjusted error includes quantization 10-bit mode p e tue ? 1 2.5 lsb 2 8-bit mode ? 0.5 1.0 differential non-linearity 10-bit mode p dnl ? 0.5 1.0 lsb 2 8-bit mode ? 0.3 0.5 monotonicity and no-missing-codes guaranteed integral non-linearity 10-bit mode c inl ? 0.5 1.0 lsb 2 8-bit mode ? 0.3 0.5 zero-scale error v adin = v ssa 10-bit mode p e zs ? 0.5 1.5 lsb 2 8-bit mode ? 0.5 0.5 full-scale error v adin = v dda 10-bit mode p e fs ? 0.5 1.5 lsb 2 8-bit mode ? 0.5 0.5 quantization error 10-bit mode d e q ?? 0.5 lsb 2 8-bit mode ? ? 0.5 input leakage error pad leakage 3 * r as 10-bit mode d e il ? 0.2 2.5 lsb 2 8-bit mode ? 0.1 1 temp sensor slope ?40 c? 25 c d m ? 3.266 ? mv/ c 25 c? 125 c ? 3.636 ? temp sensor voltage 25 cdv temp25 ?1.396? v 1 typical values assume v ddad = 5.0v, temp = 25c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh ? v refl )/2 n 3 based on input pad leakage current. refer to pad electricals. table a-9. 5 volt 10-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions c symb min typ 1 max unit
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 307 a.9 internal clock generation module characteristics table a-10. icg dc electrical specifications (temperature range = ?40 to 125 c ambient) characteristic symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0v, 25 c or is typical recommended value. max unit load capacitors c 1 c 2 see note 2 2 see crystal or resonator manufacturer?s recommendation. feedback resistor low range (32k to 100 khz) high range (1m ? 16 mhz) r f 10 1 m m series resistor low range low gain (hgo = 0) high gain (hgo = 1) high range low gain (hgo = 0) high gain (hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? 0 100 0 0 10 20 ? ? ? ? ? ? k icg extal xtal crystal or resonator r s c 2 r f c 1
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 308 freescale semiconductor a.9.1 icg frequency specifications table a-11. icg frequency specifications (v dda = v dda (min) to v dda (max), temperature range = ?40 to 125 c ambient) num c characteristic symbol min typ 1 max unit 1 oscillator crystal or resonator (refs = 1) (fundamental mode crystal or ceramic resonator) low range high range high gain, fbe (hgo = 1,clks = 10) high gain, fee (hgo = 1,clks = 11) low power, fbe (hgo = 0, clks = 10) low power, fee (hgo = 0, clks = 11) flo fhi_byp fhi_eng flp_byp flp_eng 32 1 2 1 2 ? ? ? 100 16 10 8 8 khz mhz mhz mhz mhz 2 input clock frequency (clks = 11, refs = 0) low range high range f lo f hi_eng 32 2 ? ? 100 10 khz mhz 3 input clock frequency (clks = 10, refs = 0) f extal 0?40mhz 4 internal reference frequency (untrimmed) f icgirclk 182.25 243 303.75 khz 5 duty cycle of input clock (refs = 0) t dc 40 ? 60 % 6 output clock icgout frequency clks = 10, refs = 0 all other cases f icgout f extal (min) f lo (min) ? ? f extal (max) f icgdclkmax ( max) mhz 7 minimum dco clock (icgdclk) frequency f icgdclkmin 8? mhz 8 maximum dco clock (icgdclk) frequency f icgdclkmax ?40mhz 9 self-clock mode (icgout) frequency 2 f self f icgdclkmin f icgdclkmax mhz 10 self-clock mode reset (icgout) frequency f self_reset 5.5 8 10.5 mhz 11 loss of reference frequency 3 low range high range f lor 5 50 25 500 khz 12 loss of dco frequency 4 f lod 0.5 1.5 mhz 13 crystal start-up time 5, 6 low range high range t cstl t csth ? ? 430 4 ? ? ms 14 fll lock time , 7 low range high range t lockl t lockh ? ? 2 2 ms 15 fll frequency unlock range n unlock ?4*n 4*n counts 16 fll frequency lock range n lock ?2*n 2*n counts 17 icgout period jitter, , 8 measured at f icgout max long term jitter (averaged over 2 ms interval) c jitter ?0.2 % f icg
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 309 18 mc9s08ac xx : internal oscillator deviation from trimmed frequency 9 v dd = 2.7 ? 5.5 v, (c onstant temperature) v dd = 5.0 v 10%, ?40 c to 125 c acc int ? ? 0.5 0.5 2 2 % c s9s08aw xx a: internal oscillator deviation from trimmed frequency 10 v dd = 2.7 ? 5.5 v, (c onstant temperature) acc int ? 0.5 1.5 % pv dd = 5.0 v 10%, ?40 c to 85 c? 0.5 1.5 pv dd = 5.0 v 10%, ?40 c to 125 c? 0.5 2.0 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. 2 self-clocked mode frequency is the frequency that the dco generates when the fll is open-loop. 3 loss of reference frequency is the reference frequency detected internally, which transitions t he icg into self-clocked mode if it is not in the desired range. 4 loss of dco frequency is the dco frequency detected internally, which transitions the icg into fll bypassed external mode (if an external reference exists) if it is not in the desired range. 5 this parameter is characterized before qualification rather than 100% tested. 6 proper pc board layout procedures must be followed to achieve specifications. 7 this specification applies to the period of time required for the fll to lock after entering fll engaged internal or external modes. if a crystal/resonator is being used as the refe rence, this specification a ssumes it is already running. 8 jitter is the average deviation from the programmed freq uency measured over the specified interval at maximum f icgout . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dda and v ssa and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 9 see figure a-9 . 10 see figure a-9 . table a-11. icg frequency specifications (continued) (v dda = v dda (min) to v dda (max), temperature range = ?40 to 125 c ambient) num c characteristic symbol min typ 1 max unit
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 310 freescale semiconductor figure a-9. typical internal oscillator deviation from trimmed frequency 5 v 3 v variable internal oscillator deviatio n from trimmed frequency 0.0 ?0.5 ?1.0 ?1.5 ?2.0 ?50 ?25 0 25 50 75 100 125 temp percent (%) device trimmed at 25 c at 3.0 v.
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 311 a.10 ac characteristics this section describes ac ti ming characteristics for each peripheral system. for detailed information about how clocks for the bus are generated, see chapter 8, ?internal clock generator (s08icgv4) .? a.10.1 control timing figure a-10. reset timing table a-12. control timing num c parameter symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. max unit 1 bus frequency (t cyc = 1/f bus )f bus dc ? 20 mhz 2 real-time interrupt internal oscillator period t rti 700 1300 s 3 external reset pulse width 2 (t cyc = 1/f self_reset ) 2 this is the shortest pulse that is guaranteed to be recogniz ed as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 1.5 x t self_reset ?ns 4 reset low drive 3 3 when any reset is initiated, internal circuitry drives the rese t pin low for about 34 bus cycles and then samples the level on the reset pin about 38 bus cycles late r to distinguish exter nal reset requests from internal requests. t rstdrv 34 x t cyc ?ns 5 active background debug mode latch setup time t mssu 25 ? ns 6 active background debug mode latch hold time t msh 25 ? ns 7 irq pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. t ilih, t ihil 100 1.5 x t cyc ??ns 8 kbipx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 x t cyc ??ns 9 port rise and fall time (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 125 c. t rise , t fall ? ? 3 30 ns t extrst reset pin
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 312 freescale semiconductor figure a-11. active background debug mode latch timing figure a-12. irq/kbipx timing a.10.2 timer/pwm (tpm) module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. table a-13. tpm input timing function symbol min max unit external clock frequency f tpmext dc f bus /4 mhz external clock period t tpmext 4? t cyc external clock high time t clkh 1.5 ? t cyc external clock low time t clkl 1.5 ? t cyc input capture pulse width t icpw 1.5 ? t cyc bkgd/ms reset t mssu t msh t ihil irq/kbip6?kbip4 t ilih irq/kbipx
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 313 figure a-13. timer external clock figure a-14. timer input capture pulse t tpmext t clkh t clkl tpmxclk t icpw tpmxchn t icpw tpmxchn
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 314 freescale semiconductor a.11 spi characteristics table a-14 and figure a-15 through figure a-18 describe the timing require ments for the spi system. table a-14. spi electrical characteristic num c characteristic 1 1 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit operating frequency master slave f op f op f bus /2048 dc f bus /2 f bus /4 hz 1 cycle time master slave t sck t sck 2 4 2048 ? t cyc t cyc 2 enable lead time master slave t lead t lead ? 1/2 1/2 ? t sck t sck 3 enable lag time master slave t lag t lag ? 1/2 1/2 ? t sck t sck 4 clock (spsck) high time master and slave t sckh 1/2 t sck ? 25 ? ns 5 clock (spsck) low time master and slave t sckl 1/2 t sck ? 25 ? ns 6 data setup time (inputs) master slave t si(m) t si(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ? ? ns ns 8 access time, slave 2 2 time to data active from high-impedance state. t a 040ns 9 disable time, slave 3 3 hold time to high-impedance state. t dis ?40ns 10 data setup time (outputs) master slave t so t so 25 25 ? ? ns ns 11 data hold time (outputs) master slave t ho t ho ?10 ?10 ? ? ns ns
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 315 figure a-15. spi master timing (cpha = 0) figure a-16. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 316 freescale semiconductor figure a-17. spi slave timing (cpha = 0) figure a-18. spi slave timing (cpha = 1) a.12 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 11 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 11 4 5 5
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 317 program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information a bout program/erase operations, see chapter 4, ?memory .? a.13 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and char acteristics of external components as well as mcu software operation all pl ay a significant role in emc performance. the system designer should consult freescale a pplications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifi cally targeted at optimizing emc performance. table a-15. flash characteristics num c characteristic symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. max unit 1 supply voltage for program/erase v prog/erase 2.7 5.5 v 2 supply voltage for read operation v read 2.7 5.5 v 3 internal fclk frequency 2 2 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz 4 internal fclk period (1/fclk) t fcyc 56.67 s 5 byte program time (random location) (2) t prog 9 t fcyc 6 byte program time (burst mode) (2) t burst 4 t fcyc 7 page erase time 3 3 these values are hardware state machin e controlled. user code does not n eed to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc 8 mass erase time (2) t mass 20,000 t fcyc 9c program/erase endurance 4 t l to t h = ?40 c to + 125 c t = 25 c 4 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale semiconductor defines typical endurance, please refer to engineering bulletin eb619, ty p i c a l endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles 10 data retention 5 5 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional in formation on how freescale semiconductor defines typical data retention, please refe r to engineering bulletin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
appendix a electrical characteristics and timing specifications mc9s08ac16 series data sheet, rev. 8 318 freescale semiconductor
mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 319 appendix b ordering information and mechanical drawings b.1 ordering information this section contains ordering information for the mc9s08ac16 series devices. see below for an example of the device numbering system. table b-1. device comparison device number 1 1 see ta bl e 1 - 1 for a complete description of modules included on each device. memory available packages 2 2 see table b-2 and ta b l e b - 3 for package information. qualification flash ram type type mc9s08ac16 mc9s08ac8 16,384 8192 1024 768 48-pin qfn 44-pin lqfp 42-pin sdip 32-pin lqfp consumer and industrial s9s08aw16a s9s08aw8a 16,384 8192 1024 768 48-pin qfn 44-pin lqfp 32-pin lqfp automotive
appendix b ordering information and mechanical drawings mc9s08ac16 series data sheet, rev. 8 320 freescale semiconductor b.2 orderable part numbering system the orderable part numbers for the mc9s08ac16 series devices varies accordi ng to the device family. refer to figure b-1 and figure b-2 for examples. figure b-1. consumer & industrial device numbering system figure b-2. automotive device numbering system mc 9 s08 ac n c xx e status - mc = consumer & industrial main memory type - 9 = flash-based core family - ac memory size (approx) - 16 kbytes - 8 kbytes temperature option - c = -40 to 85 c - v = -40 to 105 c - m = -40 to 125 c package designator two letter descriptor (refer to ta b l e b - 2 ). pb free indicator - e = pb free s 9 s08 aw n a e0 c xx status - s = auto qualified main memory type - 9 = flash-based core family - aw memory size (approx) - 16 kbytes - 8 kbytes mask set identifier - alpha character references wafer fab. - e = chandler - numeric character identifies mask revision. temperature range - c = -40 to 85 c - v = -40 to 105 c - m = -40 to 125 c package designator two letter descriptor (refer to ta bl e b - 3 ). device version
appendix b ordering information and mechanical drawings mc9s08ac16 series data sheet, rev. 8 freescale semiconductor 321 b.3 mechanical drawings this following pages contain mechan ical specifications for mc9s08ac 16 series package options. see the following tables for the document numbers that correspond to each package type. table b-2. mc9s08ac16 and mc9s08ac8 consumer & industrial package information pin count type designator document no. 48 qfn fd 98arh99048a 44 lqfp fg 98ass23225w 42 sdip b 98asb42767b 32 lqfp fj 98ash70029a table b-3. s9s08aw16a and s9s08aw8a automotive package information pin count type designator document no. 48 qfn ft 98arh99048a 44 lqfp ld 98ass23225w 32 lqfp lc 98ash70029a

mc9s08ac16 rev. 8, 11/2009 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc. 2007-2009. all rights reserved.

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